TE0720 fuse programming

[denial]

Hi,
we are currently facing the problem that current Vivado versions want the Zynq to be in JTAG boot mode for programming the fuses.
I know from another thread in the forum that JTAG boot mode is not supported. Is this still the case or has there been a firmware update
to the CPLD to somehow request this mode? The MIO5 pin is connected to the CPLD, so it should in theory be possible to do this.

Maybe even better would be the addition of a register in the CPLD to take control of the JTAG signals between the CPLD and the Zynq.
Xilinx provides the XilSKey library in source code that is able to program the fuses if the JTAG pins are connected to MIO pins.
One could change that library to read and write a register in the CPLD over MDIO instead of using the MIO GPIO registers.
With that solution no Vivado and no special carrier board would be needed during production.


Btw., thanks for the update to the TRM.

[JH]

Hi,
please send a email to support@trenz-electronic.de, I can send you binary with JTAG boot mode selectable. Please tell me also your whole TE article number (or the serial number) and which combination of boot mode you prefer with boot mode pin (JTAG/QSPI or SD/JTAG)
br
John

[denial]

Our customer considers adding a GPIO controller to their board to program the PL fuses from the PS during production...
No chance to convince you to add access to the PL JTAG pins through an MDIO register to the next CPLD firmware revision?

[JH]

Hi,
with newest CPLD Revision on TE0720, you can change boot mode to JTAG only over PGOOD Pin (in case your carrier support this):
https://wiki.trenz-electronic.de/display/PD/TE0720+CPLD#TE0720CPLD-BootMode
https://wiki.trenz-electronic.de/display/PD/4+x+5+SoM+Integration+Guide#id-4x5SoMIntegrationGuide-4x5ModuleControllerIOs
alternatively temporary over a running design and MDIO interface with reboot:
https://wiki.trenz-electronic.de/display/PD/TE0720+CPLD#TE0720CPLD-CRregistersaccessmethods

Binaries for new CPLD Version are available on the download area, here are some instruction how you  can update CPLD:
https://wiki.trenz-electronic.de/display/PD/TE0720+CPLD+Firmware
br
John

[denial]

I was referring to the second paragraph of the initial post. The first paragraph was about JTAG boot. The second paragraph was about simplifying production by not connecting to JTAG from outside the module at all.

Of course this makes sense only if Trenz ships the modules with a CPLD firmware that is able to do that.

[JH]

Hi,
I can share CPLD Firmware source code, in case you want to modify it by yourself. Send Email to support@trenz-electronic.de
Alternatively (I think it is maybe better solution for you), use bscan primitive from PL to get access to JTAG chain.
https://support.xilinx.com/s/question/0D52E00006hpMVUSA2/how-to-use-bscane2-and-bscan2jtag-ip-to-access-own-tap-through-primary-fpga-jtag-pins?language=en_US

Br
John

[denial]

As I wrote, production is not simplified if we have to connect to JTAG to program the CPLD instead of having to connect to JTAG to program the FPGA fuses.

BSCAN has TMS and TCK as outputs. It is for adding a device to the JTAG chain, not for controlling the chain.

[JH]

Hi,

Code: [Select]

As I wrote, production is not simplified if we have to connect to JTAG to program the CPLD instead of having to connect to JTAG to program the FPGA fuses.sorry I misunderstand you. I expected some GPIO Controller which was running on Zynq PL....

Newest CPLD Firmware allow JTAG only boot mode with configuration B2B configuration signal setup. In case you must adjust timing, than you must try out, but this can also happens without CPLD. New CPLD Firmware has max path length constrain for JTAG signals. Changing HW to bypass CPLD for JTAG without multiplexing is unfortunately not a option for this series.
br
John