connect TE0820 JTAG with a JTAG verilog design

[aymand]

Hello, I have TE0820-03 on TE0703-04,

I have a design with a JTAG interface, that I want to program to the FPGA, my question is can I send data through the mini-usb interface -which is connected to FTDI2232h- to the programmed FPGA, and any tips on how to do it?

[JH]

Hi,
simple use Vivado and Vitis. Easier than program over JTAG is to generate final boot.bin and boot from SD. Because your bitstream only inbcludes PL part, PS configuration is included into the fsbl (which depends from your xsa export from vivado to Vitis).
We offer Reference Designs and some additional notes to Xilinx(AMD) Documentation:
https://wiki.trenz-electronic.de/display/PD/TE0820+Test+Board
https://wiki.trenz-electronic.de/display/PD/Xilinx+Development+Tools

br
John

[aymand]

Hi John,
sorry maybe I wasn't clear. I wanna use the JTAG to feed continuous data to the design after it's been programmed the first time. I know we can connect verilog design ports to the carrier pins, is it possible to connect the verilog port to this JTAG bus? Especially that they're not routed to the carrier J1 and J2 pins.

[JH]

Hi,
yes it's possible.either you use Xilinx axi master (you can controll IP over Vivado TCL command shell) or Xilinx VIO Core:
https://www.xilinx.com/products/intellectual-property/jtag_to_axi_master.html
https://www.xilinx.com/products/intellectual-property/vio.html

You can also get direclty access to JTAG:
https://docs.xilinx.com/r/en-US/ug974-vivado-ultrascale-libraries/MASTER_JTAG
br
John

[Antti Lukats]

you are still not clear enough. I guess you want to use JTAG to feed data to your verilog design.

This is possible, but you do not have direct access to JTAG pins, you need to use Xilinx BSCANE2 primitive. Then you can get data from JTAG into your design.