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TE0715 boot mode from Linux console

Started by andreea, January 27, 2023, 10:23:11 AM

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I am currently working on an electronic design featuring TE0715-04-71I33A module and I am facing some issues communicating with the CPLD via i2c bus.

What I am trying to do is to change the SoC boot mode to JTAG/SD by using the i2c commands provided in TE0715 CPLD Firmware section on the wiki page The idea is to reprogram the QSPI memory with the JTAG on my custom board.

Currently I have been able to do it by changing PGOOD and MODE by Hardware, connecting both pins directly to GND but this is not an option for the final design.

Reviewing the schematics I found out that CPLD is connected to i2c1 on Zynq PS along with other devices such as clock generator, eeprom, rtc... So far I was able to successfully detect i2c1 bus on my PetaLinux but the CPLD doesn´t appear on the list of connected devices (the others do..). Is there an additional configuration required on my device-tree or some other part of the image that I have missed?

My current i2c configuration in system-user.dtsi:

&i2c1 {
    clock_frequency = <100000>;
    rtc@6F {        // Real Time Clock
        compatible = "isl12022";
        reg = <0x6F>;
    eeprom: eeprom@50 {
        compatible = "atmel,24c08";
        reg = <0x50>;

I also have tried to reprogram the Lattice CPLD with the .jed file provided on wiki for PCB Revision Support REV04 (the revision suggested for TE0715-04-71I33A in TE0715 Reference Design but with not much luck. Lattice Diamond programmer gives me an error regarding the Device ID not matching. I skip the error and reprogram the device anyway but i still can´t reach the CPLD via i2c. Just to clarify, I use TE1002 board for CPLD reprogramming through J10 connector, and I configure DIP-Switches accordingly (JTAGEN low, M_JTAG high, FMC_JTAG low)..

Any idea of what could be missing?

Many thanks


you must maybe update your CPLD. CPLD Update was not so longe ago:
Update Instructions:
--> unfortunately it's  only possible with some of our carrier with special firmware for carrier CPLD (see CPLD Update of these carriers)


Hi Jon,

Thank you very much for your help.

I also contacted Trenz via mail and your colleague Mohsen suggested basically the same solution. My Idea is to reprogram the CPLD using the JTAG connector on my custom board and using a Lattice all modules programming cable and setting JTAGEN to high. Hopefully I will be able to update the CPLD.

If not, Mohsen suggested to use the TEF1002 carrier board with a the MAX10 CPLD adapted to TEF1002.

kind regards



QuoteI also contacted Trenz via mail and your colleague Mohsen
I know :-) In general it's enough to write either forum or support email, not both (if possible). Email is sometimes easy to share things, but forum can also help other people or find the info if they have the same problems.