Author Topic: TE0720 custom carrier / 2nd Ethernet (TE0706 based) (Read 736 times)

bigguiness · « **on:** February 09, 2023, 05:02:25 PM »

I have had great success with my custom carrier board for the TE0720.

Now I'm trying to implement the 2nd Ethernet port, based on the TE0706 design. I have a couple questions.

This is what I have done so far to add the 2nd Ethernet.
1) Enabled the Zynq Ethernet 1 and MDIO, both on EMIO
2) Enabled the Zynq FCLK_CLK1 @ 200 MHz (FCLK_CLK0 @ 100 MHz is used for some other AXI peripherals in the design)
3) Added the Gmii to Rgmii IP to the design
4) Connected the Gmii to Rgmii MDIO_GEM, GMI, tx_reset, rx_reset, and clkin as in the reference design
5) Connected the Gmii to Rgmii MDIO_PHY and RGMII to the external pins
6) Connected the Zynq ENET1_EXT_INTN to the external pin
7) Added a Constant IP and connected it to the extern ETH_CONFIG pin

I don't need the Labtools Frequency Counter or VIO (I think) so I connected the Gmii to Rmii status outputs to a Concat IP and fed the output back to an AXI_GPIO in my design. This will, hopefully, allow me to readback the status as GPIO inputs bits.

Questions:

What is the Constant IP for ETH_CONFIG supposed to be set as? What does this do?

How should I handle the ETH_RST signal to the 2nd PHY? In the reference design it is driven by a Utility Vector Logic that is connected to the Processor System Reset peripheral_aresetn[0:0] and the VIO probe_out[0:0].

Do I need to do anything with the 125MHz clock coming from the PHY? I think this is the gmii_clk_0 signal in the reference design. In that design it's only used by the Labtools Frequency Counter.

I'm sure I am missing something else, especially how to get it all working correctly in Petalinux. Any pointers?

Thanks!

bigguiness · « **Reply #1 on:** February 09, 2023, 05:13:41 PM »

Oh, I just noticed this on https://wiki.trenz-electronic.de/display/PD/TE0720+ETH0706

The _i_eth1.xdc constraints shows all the Bank 34 pins going to the external PHY are set to IOSTANDARD LVCMOS33. The schematic for the TE0706 says "B34 -> 1.8V" and that is how the JB2 pins 2 and 4 are connected.

Regards

bigguiness · « **Reply #2 on:** February 10, 2023, 05:36:25 PM »

I have done my best guess to hook up the 2nd Ethernet of the Zynq in my Vivado block diagram.

I think the ETH_CONFIG pin sets the PHY address. I have it connected to a Constant '1'.

I'm still not quite sure what to do with the ETH_RST signal. For now I have it coming from a Utility Vector Logic that is an AND of the Proessor System Reset periperal_aresetn[0:0] signal and a Constant '1'. If a way to manually reset the PHY is necessary, I would like to add a bit to my AXI_GPIO outputs but I'm not sure how to do that.

It doesn't look like I need to do anything with the 125MHz clock signal coming from the PHY.

The design does the Synthesis, Implementation, and Generate Bitstream successfully.

I then updated Petalinux with the new hardware design (petalinux-config -- get-hw-description ../).

I added the &gem1 device tree information to my system-user.dtsi.

Then I rebuilt Petalinux and tried booting my system.

The 2nd Ethernet port is not found during the boot. I checked /proc/device-tree and found the 2nd Ethernet node but the status is 'disabled'. The 1st Ethernet node is 'okay':

News:

Author Topic: TE0720 custom carrier / 2nd Ethernet (TE0706 based) (Read 736 times)