TE0725 error when using IO_L12P_T1_MRCC_34 as clock input

[qojote]

Hi,
I have created a custom carrier board for my TE0725 FPGA module which features an external crystal. According to the schematic the pin B34_L12_P (T5) is named as IO_L12P_T1_MRCC_34 and should be usable as Multi-Region-clock input like shown in the picture attached. However when i try to use this pin as in put for a clocking wizard i am getting the error below. I am using Vivado 2022.2. Can you please help me to fix that isssue?

[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
   < set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets coala_design_i/clk_wiz_3/inst/clk_in1_coala_design_clk_wiz_3_0] >

   coala_design_i/clk_wiz_3/inst/clkin1_ibufg (IBUF.O) is locked to IOB_X1Y76
    coala_design_i/clk_wiz_3/inst/mmcm_adv_inst (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X1Y2

   The above error could possibly be related to other connected instances. Following is a list of
   all the related clock rules and their respective instances.

   Clock Rule: rule_mmcm_bufg
   Status: PASS
   Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
    coala_design_i/clk_wiz_3/inst/mmcm_adv_inst (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X1Y2
    and coala_design_i/clk_wiz_3/inst/clkf_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

[Waldi3141]

Hi qojote,

can you show me your constraints for that pin?

Also, have you tried to make that connection within our latest reference design 2021.2 ?
https://wiki.trenz-electronic.de/display/PD/TE0725+Reference+Designs
You can see how we connected the onboard sys_clock(P17) there.

So far we haven't updated our designs to Vitis version 2022.2, so the issue could also be with the newer version u are using.

regards
Waldi

[qojote]

Hi,
I have attached a simple example. In the meantime i have started to study the "7 Series FPGAs Clocking Resources User Guide". I am almost certain, that the problem is triggered because i am using a two-input MCMM with the onboard system clock on bank 14 and a MRCC clock on bank 34?
BR

[Waldi3141]

yep that is seems to be the problem. I was able to build your design after i disconnected the second clock clk_crystal (clk_in2) from clk_wiz_0.
good luck!