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TE0712 SI5338-Factory Configuration

Started by GuinnessTrinker, December 21, 2022, 01:54:32 PM

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I am starting to develop a MicroBlaze-Design based on your Reference "TE0712-test_board-vivado_2021.2*".

I expect Clockgeneration for MicroBlaze comes out of MIG ("ui_clk") (100 MHz).
MIG is configured to use sys_clk (Pins configured inside mig.pj) as source.

sys_clk comes from Pins H4/G4 <- SI5338A-Clk3

According to your TRM

Clk3 is configured to 50 MHz by factory-settings.

Is this reliable for the next future?

I would like to minimize my Design and not using mb_mcs to configure SI5338A.

In your reference-design the "msys_bd.tcl" lines 334 ff. constraints sys_diff_clock to be 100 MHz.

Is it a bug?


Hello GuinnessTrinker,

CLK3 -> 50 MHz - LVDS18, this clock wont change in the near future. With the new Revision 03 of TE0712 the Si5338 does not even have to be programmed in your design. With revision 03 the default frequencies are like the programmed frequencies on revision 1 and 2.

We updated the table:

If ure using a Rev01 or Rev02 Module and dont want to configure the SI5338, you will only have the Clocks CLK1A, CLK2 and CLK3.

For sys_diff_clock to be 100MHz is wrong, thats a mistake, either set by vivado per default or just mistakenly put in. It is actually 50MHz. Important is, that 50MHz is set in the MIG IP, which it is at the "Memory Options" -> "Input Clock Period".


Thanks a lot!

That makes my life much easier.