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FSBL too slow for PCIe

Started by koen_Schoutens, September 28, 2022, 03:20:43 PM

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I am using a TE0715 module with the TEF1002.
Using the PCIe connector of a ATX power supply, we cannot get the enumeration to work. Measuring the PGOOD, we see a glitch which sometimes results in the ZYNQ going into Secure lockdown.
By patching the cpld with the following:
RESIN <= BUTTON; -- SoM low active reset
RESIN <= BUTTON and PGOOD; -- SoM low active reset
We can ignore this glitch.
IS this a problem found by Trenz?

The main issue is, the FSBL is very slow. When booting from the SD card, it takes about 1 second to program the PL part (by measuring the FPGA_DONE pin) Using QSPI this can be halved (as expected).
Have you guys found the same issue?


you use module as end device? That's always a problem on nearly alle FPGA/SoCs...Easiest way ist to stop your PC on bios, until FPGA starts. In this case enumeration is in correct order.
Or you must modify Xilinx FSBL (remove all unnecessary steps) and also your bitstream (use partial reconfiguration, fist only PCIe core...later load other parts) --> make as small as possible...
You can also check Xilinx user guides for this topic.