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Timing constraints file for TE0710 periphery

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toka:
Hello,

is there a timing constraints file for the periphery on the TE0710 board available? I checked the board files and couldnt find anything.

Waldi3141:
Hello toka,

there is no dedicated timing constraint file for the periphery. For what timing constraints exactly are you looking?

best regards

Waldi

toka:
I am looking for the constraints of the input clock and the periphery like SPI flash, DDR, Ethernet. For my project, I will use additional periphery, ADC and DAC and will introduce timing constraints on these signals, so I was asking myself why there is no constraints file especially for the module.

Waldi3141:
i recommend you to start your design with our reference design. DDR, SPI, Ethernet and other peripheral are already implemented there.
https://wiki.trenz-electronic.de/display/PD/TE0710+Test+Board

All the used IOs in our reference design that are not constraint in the _i_io.xdc constraint file are constraint in the according board files -> part0_pins.xml. There you also can find the 100Mhz sys_clock which is connected to the FPGA Pin F4 with IOstandard SSTL15.
The interfaces defined in the board.xml file can be seen in Vivado > IP Integrator in the Board tab. They can be drag&dropped into the Block Design and should then appear orange in the board tab.

For all other IOs you want to use i advise you to look into the schematic.
https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0710/REV02/Documents

toka:
I am already using the reference design.

In the part0_pins there are no timing constraints for the periphery signals.

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