Author Topic: Timing constraints file for TE0710 periphery  (Read 310 times)

toka

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Timing constraints file for TE0710 periphery
« on: September 13, 2022, 05:19:15 PM »
Hello,

is there a timing constraints file for the periphery on the TE0710 board available? I checked the board files and couldnt find anything.

Waldi3141

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Re: Timing constraints file for TE0710 periphery
« Reply #1 on: September 14, 2022, 11:29:36 AM »
Hello toka,

there is no dedicated timing constraint file for the periphery. For what timing constraints exactly are you looking?

best regards

Waldi

toka

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Re: Timing constraints file for TE0710 periphery
« Reply #2 on: September 14, 2022, 11:44:22 AM »
I am looking for the constraints of the input clock and the periphery like SPI flash, DDR, Ethernet. For my project, I will use additional periphery, ADC and DAC and will introduce timing constraints on these signals, so I was asking myself why there is no constraints file especially for the module.

Waldi3141

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Re: Timing constraints file for TE0710 periphery
« Reply #3 on: September 14, 2022, 12:34:29 PM »
i recommend you to start your design with our reference design. DDR, SPI, Ethernet and other peripheral are already implemented there.
https://wiki.trenz-electronic.de/display/PD/TE0710+Test+Board

All the used IOs in our reference design that are not constraint in the _i_io.xdc constraint file are constraint in the according board files -> part0_pins.xml. There you also can find the 100Mhz sys_clock which is connected to the FPGA Pin F4 with IOstandard SSTL15.
The interfaces defined in the board.xml file can be seen in Vivado > IP Integrator in the Board tab. They can be drag&dropped into the Block Design and should then appear orange in the board tab.

For all other IOs you want to use i advise you to look into the schematic.
https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0710/REV02/Documents

toka

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Re: Timing constraints file for TE0710 periphery
« Reply #4 on: September 14, 2022, 02:25:00 PM »
I am already using the reference design.

In the part0_pins there are no timing constraints for the periphery signals.

JH

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Re: Timing constraints file for TE0710 periphery
« Reply #5 on: September 14, 2022, 05:54:49 PM »
Hi,
vivado generate some of the timing constrains also from the block design --> Parameter of the Input buffer...
DDR setup is included into the mig project.
Constrains itself can be also add to IPs or separate xdc....so there are many points where you can add timing constrains....

IO trace length constrains are no set because traces are very short or signals are slow.

You can run simple final timing report to see which timing constrains are set and automatically propagated .
br
John

toka

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Re: Timing constraints file for TE0710 periphery
« Reply #6 on: September 14, 2022, 07:25:36 PM »
Is there no requirements on the timing properties of the periphery, like delay min and max times?

JH

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Re: Timing constraints file for TE0710 periphery
« Reply #7 on: September 14, 2022, 07:50:19 PM »
depends on the interfaces and traces length....in case of this one board components(DDR, QSPI) and slow interfaces (I2C, UART) it's not needed.
br
John