Flash programming issue on TE0813

[fpga2000]

I am using a TE0813 with x4 QSPI attached. I am trying to program an image into the flash. I have created a boot image with my FSBL, bitstream and application elf. I then use the program flash dialog in Vitis to program the board. But I am getting an error regarding u-boot. I am not sure why its trying to run u-boot. Thanks

Code: [Select]

****** Xilinx Program Flash
****** Program Flash v2021.1 (64-bit)
  **** SW Build 1933 on 2021-06-09-14:19:58
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
 
 
Connected to hw_server @ TCP:127.0.0.1:3121
 
Retrieving Flash info...
 
Initialization done
Using default mini u-boot image file - C:/Xilinx/Vitis/2021.1/data\xicom\cfgmem\uboot\zynqmp_qspi_x1_single.bin
===== mrd->addr=0xFF5E0204, data=0x00000000 =====
BOOT_MODE REG = 0x0000
Downloading FSBL...
Running FSBL...
Finished running FSBL.
Problem in running uboot
Flash programming initialization failed.
 
ERROR: Flash Operation Failed

[JH]

Hi,
did you changed boot mode to JTAG?
Did you select correct assembly variant? --> Memory settings and QSPI settings are correct?

And minimum your QSPI settings are wrong --> ist must be x4 dial parallel (you must have the correct setup in your vivado ZynqMP IP (for your XSA export and when you select the flash) not single qspi x1 like you has selected

Which carrier did you use?
Basic configuration is here:
https://wiki.trenz-electronic.de/display/PD/TE0813+Test+Board


br
John

[fpga2000]

Hi John

I have JTAG mode selected. The QSPI pins seem fine in Vivado. I tried programming with x4 dual stacked mode but its still giving the error. Here is the xparameter.h file values for the flash

Code: [Select]

#define XPAR_PSU_QSPI_0_IS_CACHE_COHERENT 0
#define XPAR_PSU_QSPI_0_REF_CLK QSPI_REF
/* Canonical definitions for peripheral PSU_QSPI_0 */
#define XPAR_XQSPIPSU_0_DEVICE_ID XPAR_PSU_QSPI_0_DEVICE_ID
#define XPAR_XQSPIPSU_0_BASEADDR 0xFF0F0000
#define XPAR_XQSPIPSU_0_HIGHADDR 0xFF0FFFFF
#define XPAR_XQSPIPSU_0_QSPI_CLK_FREQ_HZ 299999939
#define XPAR_XQSPIPSU_0_QSPI_MODE 2
#define XPAR_XQSPIPSU_0_QSPI_BUS_WIDTH 2
#define XPAR_XQSPIPSU_0_IS_CACHE_COHERENT 0
I am thinking that maybe there is something wrong with my bin file? I am a bit confused why its trying to use u-boot as I am not using Linux. Or does it use that anyway?

[JH]

hi,
 dual parallel not dual stack.

you see Xilinx microUboot. For Zynq/ZynqMP Xilinx use some small Uboot which copies files to the flash. this microuboot need correct DDR and flash settings, which comes from FSBL, which you select for programming...or SDK use script version of the FSBL. This FSBL depends on your XSA file which depends on your PS Zynq IP setup which depends on your HW. Some of the HW comes from trenz (in your case only QSPI and DDR), all other periphery depends on your carrier....and your PS-PL design....

br
John