Trenz Electronic Products > Trenz Electronic FPGA Modules

TE0803: Migration from TE0803-01-04CG-1EA to TE0803-03-5DI24-A

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daniel97:
Dear Trenz Team,

I am working on porting Linux from TE0803-01-04CG-1EA SoM to TE0803-03-5DI24-A SoM.
I use the same custom carrier board for both SoMs.
Linux is built with Yocto, including all required Xilinx Layers and the devicetree generation based on the provied xsa archive.

I use (of course) a different Vivado projects for both variants with the designated Trenz Board Files.
Both Designs using Gem0 via MIO 26...37 and are connected to an 100Mbit Ethernet PHY (TI DP83822i).
MDIO is routet through the PL via EMIO.
Both designs are using the same constraints for the MDIO and PHY Reset.

The problem I face is the bring up of the Ethernet Port.
With the EV, the interface is not configured properly, also a link is not detected by Linux. (LEDs on the Port indicates that the link is established at 100Mbit).
In case of the CG SoM, the Port works fine.

I attached the Error Message during boot. This Message is thrown by the Xilinx macb Ethernet driver.

It is not possible to read PHY registers with Phytool at the EV (With the CG it is, more Attachaments can be provided..)
Because of these messages I assume the MDIO is not working fine. Nevertheless the PHY is correctly identified during boot.

I am contacting you here to ask for any differences in the (Hardware) Design between those two Board Variants.
Are there any dfferencies regarding pull up's or anything else that could cause the Error?
Do you maybe know other differencies regarding the Xilinx Device, e.g. DMAs which might help here?

I have checked the following things before writing this post:

* Devicetree: DMA adresses are the same
* Pin Mapping (with Trenz Excel Sheet https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Pinout): Same for both variants
* Trenz Revision Changes (https://wiki.trenz-electronic.de/display/PD/PCN-20180817+TE0803-01+to+TE0803-02+Hardware+Revision+Change): Didn't find anything what could be related to the issue
Many thanks for any help and hints, which might help to fix this issue!
Daniel



 

JH:
Hi,

--- Quote ---based on the provied xsa archive.
--- End quote ---
You use your own xsa from your vivado projects, correct? XSA contains also memory information. Different Memory is used on both board. When you use the same xsa, maybe your linux is not configured correctly. "Can not allocate memory" looks like some problem with memory....


--- Quote ---MDIO is routet through the PL via EMIO.
--- End quote ---
Why did you not use MIO? But no matter, in this case PL must be programmed with valid bistream which forward MDIO signals to you phy. Can you check also if  uboot recognise your eth phy on the carrier? If not, maybe this is the second problem...


--- Quote ---Trenz Revision Changes (https://wiki.trenz-electronic.de/display/PD/PCN-20180817+TE0803-01+to+TE0803-02+Hardware+Revision+Change): Didn't find anything what could be related to the issue
--- End quote ---

this is from 01 to 02 and you has 03 revision now:
https://wiki.trenz-electronic.de/display/PD/PCN-20190107+TE0803-02-*-*+to+TE0803-03-*-*+Hardware+Revision+Change

and you has additionally changed assembly option....so there are more changes than PCB Revision only.
we provide different board files with correct memory configuration in our reference designs, in case you use same memory setup on both modules, please check these files (open Reference design for your TE0803-03-5DI24-A and compare Memory settings with your project for this variant)
.
br
John

daniel97:
Hey John,

thanks for your answer and the further Questions!


--- Quote ---You use your own xsa from your vivado projects, correct? [...] When you use the same xsa, maybe your linux is not configured correctly.
--- End quote ---

Yes, I use the xsa archives from my own two different Vivado projects. Each Vivado project is based on the designated Trenz Board Files for the specific variant (The version of my Board Files for the EV differs from the version of the current Trenz reference Design. Mines were older, see below for my next try).
Each of the xsa archives is passed to Yocto and selected for the different MACHINEs in Yocto.



--- Quote ---Why did you not use MIO?
--- End quote ---

I don't use the MIOs for MDIO, because there were no more free MIO Pins available (The PCB with the Ethernet Port is an extention to our existing carrier board, which provides a mix of PS and PL Pins on a B2B-Connector for future adaption,which we now used).


--- Quote ---this is from 01 to 02 and you has 03 revision now
--- End quote ---

Thank you for remembering me. I also read this article before, but forgot to mention it in the post. The memory obviously changed, which might cause the error in combination with my ouddatetd board files (see below).

Thanks for mentioning the Trenz Reference Design. I downloaded and created the project for device number 63 (TE0803-03-5DI21-A). The Memory Settings are the same, but the board file version used in the reference design is newer compared to mine.

I created a new Vivado project based on the same board files as the reference design, then I went through the whole Yocto workflow again.
All in all that didn't help. The problem is still the same. (See attached Boot log)


--- Quote ---Can you check also if  uboot recognise your eth phy on the carrier?
--- End quote ---

In both cases (CG and EV) U-Boot does not recognise the PHY. The U-Boot tools mii and mdio both do not see it. Nevertheless in the CG Case the Phy works after that in Linux and I can read the registers with Phytool. In case of the EV I can not read them. (See the attached screenshots)

I will now try to use as much of the working CG project for the EV Design.
Perhaps the point in time when the PHY reset occurs is slightly different and may cause the difference.
I will use the board files from the Reference Design for that.

I will also be in holiday next week and I might need a license renewal to create the bitstream for this new project, so please excuse a late feedback from my side.
I will let you know how it goes as soon as possible.

Daniel

JH:
Hi,
can it be that you has different problems?
on one of your first logs, linux has memory allocation problem...but now Uboot can't find phy over MDIO, so either phy address is wrong or your connection the the PHY over PL or maybe your phy is in reset?
br
John

daniel97:
Hi,

sorry for my delayed answer...

I now managed to bring up the PHY with the EV variant.
While comparing my CG Vivado project and my EV Vivado project the RAM settings were the only major difference.

The PHY works with the EV, when I change the RAM settings in Vivado from 4GB, which is the default set by the EV Board Files, to 2GB only.
The devicetree generated by the Xilinx Devicetree Generator during the Yocto build is changing accordingly (See attached screenshots).

In both working Cases (CG and EV) U-Boot tells

--- Code: ---Net:   MDIO bus not found ethernet@ff0b0000
No ethernet found.

--- End code ---

during boot.

Nevertheless the PHY is working fine after the kernel is bootet and I can also read the PHY Registers with phytool.

I checked all the address spaces for the GEM0, 2GB and 4GB memory from the devicetree from the reg properties. The addresses of the memory and the GEM0 do not collide.
The 4GB memory variant uses 2 Blocks of 2GB, one from 0x0 to 0x7ff0000 and one from 0x800000000 to 0x880000000.
The address space of GEM0 lies in between these two blocks, but does not collide (0xff0b0000 to 0xff0b1000).

Do you have any idea or comment on this?

Many thanks!
Daniel

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