Boot TE0720 problem on a custom carrier

[joaquinlc]

Dear Sirs,
We have developed a custom carrier board for TE0720. Our design is based mainly on carrier TEB0707 design.
I have a technical question that I would appreciate your help.
The boot of the board is not working properly. Very often green led D4 (DONE) of TE0720 stay on and does not allow to be programmed.
If we turn on/off the power supply several times, then we get this led stay off and then we can work.
I presume that had to do with the signal RESIN. On carrier TEB0707 this signal is managed by the CPLD, but in our custom carrier there is not CPLD and we manage this signal with a RC circuit, please see attached schematic images. On the images, RESETn is connected to RESIN signal of the module.
Do you agree that the problem could come from RESIN signal?
A the moment, with the RC circuit I get a delay of aprox 2ms between the 3V3 and the on of RESIN. I could increase this delay with a higher capacitor. Is there any time specification for the RESIN signal?
Would be a good idea to connect RESIN signal to PGOOD output of the module?
If you need more details do not hesitate to ask for them.
Thanks in advance,
Joaquin.

[JH]

Hello,
there  are 3 LEDs on the module, can you tell me the state of all 3 LEDs in case it doesn't boot?
https://wiki.trenz-electronic.de/display/PD/TE0720+TRM#TE0720TRM-MainComponents
https://wiki.trenz-electronic.de/display/PD/TE0720+CPLD#TE0720CPLD-On-boardLEDs

Do you boot from SD or QSPI?

What's with the other controller signals? Especially NOSEQ, EN1 and MODE(Boot Mode which is connected to your SD CD Pin). How they are connected?
How did you enable periphery voltage? VCCIO13, 33 and 34. Especially Bank 34, which is need to power up the module completely.

RESETn is connected to RESIN signal of the module.
Do you agree that the problem could come from RESIN signal?

I didn't believe that at the moment. On TE0706 we connect it only to push button without capacitor.

Would be a good idea to connect RESIN signal to PGOOD output of the module?

No, use them only for monitoring.
PS: We have updated our CPLD Firmware (new version is available on the download area). PGOOD has double functionality now. Output is still power good and as input as additional boot mode pin (you can set JTAG only boot mode with new firmware directly (in case you can control it with the carrier, change boot mode via software on zynq is also possible now)):
https://wiki.trenz-electronic.de/display/PD/TE0720+CPLD#TE0720CPLD-BootMode
We have done this to solve qspi programming problems with newer Vivado versions (20.x or newer):
https://wiki.trenz-electronic.de/display/PD/AVN-20220506+4+x+5+modules+controller+IOs+redefinition+and+CPLD+updates

br
John

[joaquinlc]

Hello John,
Thank you for yout support.

Regarding leds:
LED2 (D5 on board), red, flashing.
LED3 (D4 on board), always on.

Regarding booting from SD or QSPI:
It happens on both.

For the control signals, we have a microswitch (see attached image Control_signals.jpg) and we can change the initial value. Actually 1-2-3 are in OFF state and 4 (EN1) is On, 3.3V.

For the power supply, there is not any special sequencing (see previous image Power_supply.JPG). 3.3V is the same as VCCIO_CA, VCCIO_CB and VCCIO_CC. All are the same signals but with different names, just to keep some compatibility between different schematics used to make our design.
Regards,
Joaquin.

[JH]

Hi,

Regarding leds:
LED2 (D5 on board), red, flashing.
LED3 (D4 on board), always on.

LED2: 50/50 duty cycle for and slow blink(QSPI mode) or fast blink(SD boot)?
Or is the duty cycle not equal (1/8 On and 7/8 off)?

For the power supply, there is not any special sequencing (see previous image Power_supply.JPG). 3.3V is the same as VCCIO_CA, VCCIO_CB and VCCIO_CC. All are the same signals but with different names, just to keep some compatibility between different schematics used to make our design.

You mean without sequencing? all Power Inputs are enabled to the same time? That's not good, in this case you will back source the module over FPGA banks, which can destroy the FPGA, maybe this will interrupted also booting.
Some notes regarding this topic: https://wiki.trenz-electronic.de/display/PD/FAQ
Point: Power sequencing for variable IO banks and connected periphery
In most case IOs should be enabled after core voltages are powered on.  Some module output voltage can be used to enable carrier power regulator for variable bank powers and connected periphery.
https://docs.xilinx.com/v/u/en-US/ds187-XC7Z010-XC7Z020-Data-Sheet
https://support.xilinx.com/s/article/37347?language=en_US


So for TE0720:
1. supply 3.3VIN and VIN (either together or at first 3.3VIN and than VIN)
2. Wait until 1.8Vout or 3.3Vout is available on the B2B connectors and enable all other variable bank powers (in your case you can use power switch for example) and IO periphery with this output voltage. Important: for TE0720, Bank34 must be supplied otherwise module will be not come ready.
Use power good signal only for monitoring. With newest firmware PGOOD can also be used as additional boot mode pin, to select more than 2 boot modes, see:
https://wiki.trenz-electronic.de/display/PD/AVN-20220506+4+x+5+modules+controller+IOs+redefinition+and+CPLD+updates

Regarding your EN1 and NOSEQ:
They have week internal pullup on the module (CPLD), so it's normally better to add also pullup on the carrier and force to zero, in case you want to disable it.


PS: You can send your schematics as pdf also to support@trenz-electronic.de and we can check it one time, if you want.

br
John

[joaquinlc]

Hi John,
Thank you for your support.
I see now the problem. I did not read properly the directions on this subjet in the TRM.

Regarding LED2, is 50/50 fast blinking (SD boot). If we remove the SD card then is slow blinking.
I send you the actual schematics to support@trenz-electronic.de. I will add in the subject "MCSERVER Schematics".
What it would be interesting for me is, once the changes be done, if you could check this new version of the schematics. Woudl it be possible? It will be available in several weeks, just to test everything before.
Regards,
Joaquin.

[JH]

Hi,

I will check your schematics during the next week and send you feedback. It's also possible to check one time your final new revision. The check usually takes 1-2 weeks, but since it is free of charge, there is no guarantee of completeness. But it helps in all if once again someone else looks at it.
PS: I send you also short note on your email.

br
John