TE0712 oscillators drift

[ame]

Hello,

I'm using two TE0712 with SI5338A feeded by (SiT8008BI) to initiate Aurora link it runs smoothly.
Then from only one of TE0712 I replace SI5338A (MGT0) by PCIE (MGT1) clock from PC. And the link do never UP with exactly the same design.

So I use labtool FrequencyMeter to mesure my PCIE clock with SI5338A  as reference clock.
Mesured PCIE clock is 99.76MHZ . So it's -2400ppm drift from 100MHz , almost 10 times more than the 300ppm specified by the PCIE spec. The pcie have also strong rms jitter.
I mesure the clock from another PC and the mesure is 99.77MHz. So SI5338A ref clock looks imprecise.

I program SI5338A to 99.76MHz to board 1, and try to sync the Aurora link with board 2 (feeded by pcie  clock) and it still do not works.

My question is, do the SI5338A feeded by (SiT8008BI +-50ppm after 1years)  is enough precise and stable to synch with a PCIE clock?
From the SI5338A datasheet yes but it seems to not be the case.
Could the clocks of the two PCs have shifted by aging? (More than 5 years PC)

Regards

PS: Aurora test summary:

-----------------------------------------------------------------------------
Aurora   |  Source CLK  MB   |  MainBoard      | ITF (always Si5338)
    OK    |   Si5338               |  125MHz          | 125MHz
    OK    |   Si5338               |  99.79MHz       | 99.79MHz
    OK    |   Si5338               |  100MHz          | 100MHz   
    KO    |   Si5338               |  99.76MHz       | 99.99MHz
    KO    |   PCIE                  |  99.79MHZ       | 100MHz
    KO    |   PCIE                  |  99.76MHZ       | 99.76MHz

[JH]

Hi,
fmeter of the reference design is not accurate enough.
It simple compare calculate clk with 2 counter (one with known and one with unkown clk). from relationship you get the result on vivado HW Manager.
It's only used to see that a clock is there with appr. frequency which you expect.


You say "I'm using two TE0712 with SI5338A feeded by (SiT8008BI) to initiate Aurora link it runs smoothly."
You use default MGT_CLK0_P/N in this case? SI5338 use default 125 MHz clk on this pin. Where everything works.

So when you change reference input in your aurora IP from MGT0 to MGT1, you must also change reference clk from 125MHz to 100MHz
--> the result are different lanerate. In case the line rate does not match, you get never a link.
--> I think this is maybe your problem when I see you picture (but when I see your final table, you had change something did you changed si5338 configuration?).

Instead of Aurora, instantiate Xilinx ibert test. Configure input clks and lane rate and export IP example. Compile this example project and start ibert on both modules, where you has this 100MHz from your PC.

Check at first if the MGT PLLs locks (if they don't lock, than you has a problem with your reference clk). If they locks, check line rate and create eye diagram of the lanes.

br
John

[ame]

Hi,
fmeter of the reference design is not accurate enough.
It simple compare calculate clk with 2 counter (one with known and one with unkown clk). from relationship you get the result on vivado HW Manager.
It's only used to see that a clock is there with appr. frequency which you expect.


You say "I'm using two TE0712 with SI5338A feeded by (SiT8008BI) to initiate Aurora link it runs smoothly."
You use default MGT_CLK0_P/N in this case? SI5338 use default 125 MHz clk on this pin. Where everything works.

So when you change reference input in your aurora IP from MGT0 to MGT1, you must also change reference clk from 125MHz to 100MHz
--> the result are different lanerate. In case the line rate does not match, you get never a link.
--> I think this is maybe your problem when I see you picture (but when I see your final table, you had change something did you changed si5338 configuration?).

Instead of Aurora, instantiate Xilinx ibert test. Configure input clks and lane rate and export IP example. Compile this example project and start ibert on both modules, where you has this 100MHz from your PC.

Check at first if the MGT PLLs locks (if they don't lock, than you has a problem with your reference clk). If they locks, check line rate and create eye diagram of the lanes.

br
John

Thanks for your reply.
Yes I configure SI5338A  from TE0712 reference design to 100MHz. The problem is from PCIE gen2 allow +-300ppm jitter  and Aurora link support only +-100ppm jitter. More most low-cost pcie-RP use SpreadSpectrumClk so I cannot feed Aurora-link from standard pcie-RP clk.

Thanks again for your help.

Alexandre.M

[JH]

Hi,
I would recommend to generate Xilinx IBERT IP for different line rates and check eye diagrams, to see quality of your channels.
Maybe a little bit slower line rate works. You can also try to adjust setup a little with IBERT to get better channel quality.Properties can be changed on Auroa IP later also.
br
John

[ame]

Hi,
I would recommend to generate Xilinx IBERT IP for different line rates and check eye diagrams, to see quality of your channels.
Maybe a little bit slower line rate works. You can also try to adjust setup a little with IBERT to get better channel quality.Properties can be changed on Auroa IP later also.
br
John

I will try it.

Thank you for your help.
Regards

[JS]

Any news about that issue?