Problem with programming TE0745 QSPI Flash

[Daniel_Kan]

Hi,
I am using a TE0745 module with the self designed carrier board. The module has OK performance while RAM programming, But It is not possible to program QSPI flash and It doesn't recognize QSPI memory on module and returns JEDEC error code as programming process log. I tried by vivado19.1+SDK and vivado19.2+vitis. Also I changed boot mode to JTAG_MODE in main.c file in src of fsbl project. I have also tried with fsbl_flash.elf downloaded from ref design of trenz and it recognized QSPI memory, confirmed there doesn't exist any hardware problem. Whould you please guide me how to solve this problem? Is it necessary to edit ps7_init or other files?
Thanks in advance

[JH]

Hi,

problem is, that it seems that Xilinx change something on the JTAG programming procedure and this does not longer work together with devices where boot mode is not jtag only.
FSBL Flash simple change boot mode for software to JTAG only an disabled DDR (this is normally not need):
https://wiki.trenz-electronic.de/display/PD/TE0745+Test+Board#TE0745TestBoard-zynq_fsbl_flash.1
--> Search for "TE Mod" on the source code to see our changes (test_board\sw_lib\sw_apps\zynq_fsbl_flash\src).
it's more or less what Xilinx has recommended here: https://support.xilinx.com/s/article/70548?language=en_US

This changes works up to Vivado 19.2. For 2020.2 you must also change boot mode to a interface where the devices doesn't find an valid image, otherwise Vivado starts fsbl from this image instead of the selected one from vivado. With 21.2 this kind of workaround does not longer works.  We start now to change our CPLD Firmware step by step to allow customer easier to select jtag only boot mode(either change definition of some of the controller signals to get more boot modes selectable or offer different kind of CPLD firmware --> replace SD boot or QSPI boot mode with JTAG only boot mode as option firmare).
 
I has wrote done, different behaviour and possible solutions for different vivado versions:
https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=105689937

br
John

[Daniel_Kan]

Hi, Dear JH

Thanks for your complete answer,
I solved the problem of programming flash based on changes in main.c file as mentioned for ref design of trenz over TE0745 module, but unfortunately my design is not capable of booting.
I think that is because of DDR initialize function in main.c file. If function is run, programming of flash is failed and if it is commented, programming of flash is successful but it is not possible to boot.
I performed a small test design by fsbl.elf of ref design that its ddr init function runs as its src files, programming and booting are without any problem but fsbl.elf is generated in petalinux and I am implementing by vivado19.1+SDK and vivado19.2+vitis on windows7/10 and fsbl.elf  is not completely matched to my original design.
and last question, is it possible my problem comes from SDK compiler flags which may cusses to not to generate the files correctly.
 
Thanks in advance for any help.

[JH]

Hi,

I think that is because of DDR initialize function in main.c file. If function is run, programming of flash is failed and if it is commented, programming of flash is successful but it is not possible to boot.

Can it be that you use the same FSBL for flash writing and booting? You need 2 different FSBL, one for Flash writing and one which is included into your Boot.bin.

is it possible my problem comes from SDK compiler flags

yes but at the moment I didn't think it's compiler problem. We use also Vitis/SDK to generate FSBL for all our variants.


br
John