Author Topic: How Xilinx_eddp_mode Change  (Read 117 times)

Jason bourne

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How Xilinx_eddp_mode Change
« on: November 23, 2022, 03:03:02 AM »
Hi guys,I'm a newbie at motion control and Linux. When I was developing with the XIILNX_EDDP suite, I had two problems:

1. I don't know where the mode in FOC_IP core is inserted;

2. And what is the Mode transition's sequence when initializing. :'(
Looking forward to your reply.

Andrei Errapart

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Re: How Xilinx_eddp_mode Change
« Reply #1 on: November 30, 2022, 11:42:48 AM »
Hi Jason Bourne,


My apologies for the late answer; for some reason I didn't get notification emails anymore.

1.
I am not really sure as what do you mean by "where the mode in FOC_IP core is inserted". The source code for the FOC HLS can be found in "IIoT-EDDP\Vitis\app_arty_7z_10\src\foc.cpp"; in the function "foc" you can see search for "Mode" to see how it is used.

When you have booted to Linux, you can use the program "focserver" to write to any register as follows:
focserver -w Mode=1
to set mode to 1, e.g. MODE_SPEED as described in the file "foc.h".

This command effectively performs masked write to the the control register. One can manually write to the control register, too. This is the first register (offset 0). Run "lsuio" to see the UIO devices, one of them is either "foc" or "xlnx,foc-". There you get the physical address of the register block. Important: parameter registers start at offset 0x40, status registers start at offset 0x80. On the Linux command line, you can use "devmem" to read and write to this address (offset by 0x40).

2. Regarding the initialization sequence, you can see one in the file "IIoT-EDDP\focserver\files\src\FocDevice.cpp", method "startMotor". When the motor was stopped before setting mode other than stopped, it runs encoder offset search routine at low motor speed by searching for the encoder reading at the moment when current in coil "A" crosses zero point. There is a small offset added, which might vary when you are using a different motor or a different encoder.

Hopefully this helps. If you have any questions, don't hesitate to ask.


best regards,
Andrei

Jason bourne

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Re: How Xilinx_eddp_mode Change
« Reply #2 on: December 01, 2022, 10:17:58 AM »
Hi Andrei Errapart´╝î
1. There is something wrong with the description in question 1, I want to express that there is a control_in pin in the IP core foc_control_v1.0 (this IP core is found on github), I want to know how the input value of this pin changes;
2. Regarding the second point, thank you for the solution you provided. I will try it after class.
Yours sincerely´╝î
Jason
« Last Edit: December 01, 2022, 10:19:54 AM by Jason bourne »

Andrei Errapart

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Re: How Xilinx_eddp_mode Change
« Reply #3 on: December 01, 2022, 01:54:12 PM »
Hi Jason Bourne,


The easiest way is to trace this signal on the Block Design. For that one just has to do the following:
1) start _create_win_setup.cmd
2) edit design_basic_settings.cmd
3) start vivado_create_project_guimode.cmd

Open Block Design, select the net routed to "control_in" and you'll see that it is connected to WR0 on the component axi_reg32_0. On the Address Editor, you'll see that the address on the AXI bus is 0x43C0_0000. Just add an offset of 0x40 to this address and write a 32-bit value to it. This register matches the register CONTROL_REG in the SDSoC design and performs same functions; see the file "IIoT-EDDP/doc/FOC_SDSoC.pdf".

To see what's in this register, simply read it.

If you have any further questions, don't hesitate to ask.


best regards,
Andrei