Trenz Electronic Products > Trenz Electronic FPGA Modules

TE0712 and TE0706 ethernet

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PEPPE:
Hello,
I'm using a TE0712 over TE0706 carrier board. I've created a version of FW testboard REV01 with Vivado 2016.4 without MCS and SC0712 (please see image attached). I ran peripheral_test (over standalone bsp) with SDK. All peripherals are OK, but the axi_ethernet_lite (I'm using the physical on the TE0712) is always FAILED. Why????

P.S.: when I generate the bitstream, I've 12 critical warnings reguarding the ethernet_lite core (see image attached)...

Thank you for the support.

Waldi3141:
Hello Peppe,

have you tried that with using the original Block Design from us? without removing anything.
Also why dont you try to use a later Vivado version with the related test_board 2021.2, some problems from earlier versions might be fixed here.

greetings

Waldi

PEPPE:
Hi Waldi,

I've some problems to install the version 2021.2 on my workstation because I haven't administrator permissions. I'll try to install vivado 2021.2 on my personal computer and I'll tell you the result. Meanwhile can I try another solution on my workstation?

Thanks

Peppe

Waldi3141:
Hello Peppe,
the MicroBlaze MCS IP, that you left out, runs the program which you can find in ...\test_board\sw_lib\sw_apps\scu_te0712\src. It configures the onBoard Clocking Chip Si5338. And this chip creates a Clock for the Ethernet PHY. So i think you need to have the MicroBlaze MCS in your Design associated with the scu_te0712.elf.
Also this stands here: https://wiki.trenz-electronic.de/display/PD/TE0712+TRM#TE0712TRM-Clocking
The Ethernet PHY needs a 50MHz Clock.

best regards!

Waldi

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