TE0820: how to use SI5338 as clock source for PL fabric

[sueaki]

Hello everyone,
Thanks in advance for your help.

I am new to hardware world and using TE0820.

The reference design works perfect on my board. The block design looks like this:


I can remove SI5338 parts and use PS as clock source like this:


My question is: is that possible using SI5338 or other clock on the board as the clock source for my design? What I want to do is like this:

Or something like this:


I tried, failed and got an error like this:

[Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
   < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets design_1_i/util_ds_buf_0/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/O] >

   design_1_i/util_ds_buf_0/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X2Y99
    design_1_i/util_ds_buf_0/U0/IBUF_OUT[0]_BUFG_inst (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y1

   The above error could possibly be related to other connected instances. Following is a list of
   all the related clock rules and their respective instances.

   Clock Rule: rule_bufgce_bufg_conflict
   Status: PASS
   Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
   used at the same time
    and design_1_i/util_ds_buf_0/U0/IBUF_OUT[0]_BUFG_inst (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y1

I am not sure what it means.

[JH]

Hi,
theoretical it works without PS, but SI5338 is not programmed by default this will done by our FSBL during booting.
So in any case you need PS.
But it's much easier to use PS-PL CLKs (you can modify PS IP). In this case it's also important to regenerate FSBL, because FSBL configures PS with configuration from XSA export. Bitstream is PL only.

Regarding your "Error" when you add the attribute(CLOCK_DEDICATED_ROUTE) which Xilinx mentions there than it's possible to generate bitstream. Problem is that you use a Port which is not recommended to use for CLK --> CLK signal must routed over fabric into the CLK network of the FPGA, which is problematic for timing calculation (but manly when you use the same CLK also on external devices...).

br
John