Trenz Electronic Products > UltraScale

TE0841 flash and DDR4

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JH:
Hi,
but DDR works with prebuilt files or?  Because you  wrote " work successfully in DDR4 test."

On your design, you must also check clocks (did you connect everything like on the reference  design?).
Check if you has enabled DDR Power in your design (this will be done via our our SC0841 IP in our reference design). Did you add this IP?
https://wiki.trenz-electronic.de/display/PD/TE0841+Test+Board#TE0841TestBoard-BlockDesign


--- Quote ---carrier is TEBA0841-02;Heatsink is using；Programmed with JTAG,FPGA work normally.
--- End quote ---
What's your external power supply and what's the current limit. Current consumption at QSPI boot and JTAG boot can be different for a short time (the time interval how everything starts up is different). If you have a short voltage drop during boot, it can happen that it aborts.
Check also your design and mcs setup, you must configure both for x4. For Vivado design, you must add this general constrains:
https://wiki.trenz-electronic.de/display/PD/TE0841+Test+Board#TE0841TestBoard-Basicmoduleconstrains

br
John

slark:
hi,
   There is a question.The Row address width in CSV file found in reference design is difference from K4A8G165WB datasheet.Refering to reference design，the capacity is not 8Gb but 4Gb.Is reference design wrong?

JH:
Hi,

--- Quote ---The Row address width in CSV file found in reference design is difference from K4A8G165WB datasheet.Refering to reference design，the capacity is not 8Gb but 4Gb.Is reference design wrong?
--- End quote ---
i must check, but prebuilt files was generated with this csv and they was running...see prebuilts
Xilinx has only this documentation and content has of the csv has changed form time to time, maybe there was some copy paste error from me.
https://support.xilinx.com/s/article/63462?language=en_US

I've holiday at the moment I can check this when I'm back.
br
John

JH:
Hi,
can you tell me which datasheet you has used?
k4a8g165wb-birc is  8Gbit:
https://semiconductor.samsung.com/dram/ddr/ddr4/k4a8g165wb-birc/

And yes row address is wrong, should be 16 (but it works also with 15). We will change to 16 for 2021.2 release, which is in preparation at the moment. Thank you for pointing out this mistake.

br
John

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