TE0841 flash and DDR4

[slark]

hello:
       I choose TE0841_40_1C V2.0,FPGA cannot boot from flash.in addition，A calibration failure occurs at DDR4 MIG IP.How to solve these two problems？

[JH]

Hi,
which TE0841 assembly version did you bough? Can you send me whole article name or serial number (small number with QR code on the module)?
Depending on assembly variant you need different settings and also additional constrains files.
We have some reference designs with prebuilt binaries:
https://wiki.trenz-electronic.de/display/PD/TE0841+Test+Board#TE0841TestBoard-Hardware
https://wiki.trenz-electronic.de/display/PD/TE0841+Test+Board#TE0841TestBoard-Download
Can you test them? In case your variant in not included until now, send me the hole article name or serial number and I tell you which one you must select.

br
John

[slark]

hi,
  The version is TE0841-02-040-1I, flash selected in vivado(2018.3)is MT25QU512A,DDR4 chips are K4A8G165WB-BIRC.The  .bit file included in Reference_Design（2019.2） work successfully in DDR4 test.The .mcs included in Reference_Design shows that the loading is successful, but it can't boot from flash.

[JH]

Hi,

The version is TE0841-02-040-1I, flash selected in vivado(2018.3)is MT25QU512A,DDR4 chips are K4A8G165WB-BIRC.The  .bit file included in Reference_Design（2019.2） work successfully in DDR4 test.

So DDR problem is solved

The .mcs included in Reference_Design shows that the loading is successful, but it can't boot from flash.

Vivado say it's still not programmed also when you power off and on and reconnect Vivado HW Manager?
Or mean you did mean with "can't boot", you did not see any output on uart or so?

Which carrier did you use? Which external power supply? Some current limit? Do you use Heatsink for the module?

br
John

[slark]

So DDR problem is solved

No,it just Microblaze step passed,and calibration failed in first DQS step with my bit file.

Vivado say it's still not programmed also when you power off and on and reconnect Vivado HW Manager?

yes

Or mean you did mean with "can't boot", you did not see any output on uart or so?

If fpga programmed,led in board chang light to dark and status register show flash initialization not complete

Which carrier did you use? Which external power supply? Some current limit? Do you use Heatsink for the module?

carrier is TEBA0841-02;Heatsink is using；Programmed with JTAG,FPGA work normally.

[JH]

Hi,
but DDR works with prebuilt files or?  Because you  wrote " work successfully in DDR4 test."

On your design, you must also check clocks (did you connect everything like on the reference  design?).
Check if you has enabled DDR Power in your design (this will be done via our our SC0841 IP in our reference design). Did you add this IP?
https://wiki.trenz-electronic.de/display/PD/TE0841+Test+Board#TE0841TestBoard-BlockDesign

carrier is TEBA0841-02;Heatsink is using；Programmed with JTAG,FPGA work normally.

What's your external power supply and what's the current limit. Current consumption at QSPI boot and JTAG boot can be different for a short time (the time interval how everything starts up is different). If you have a short voltage drop during boot, it can happen that it aborts.
Check also your design and mcs setup, you must configure both for x4. For Vivado design, you must add this general constrains:
https://wiki.trenz-electronic.de/display/PD/TE0841+Test+Board#TE0841TestBoard-Basicmoduleconstrains

br
John

[slark]

hi,
   There is a question.The Row address width in CSV file found in reference design is difference from K4A8G165WB datasheet.Refering to reference design，the capacity is not 8Gb but 4Gb.Is reference design wrong?

[JH]

Hi,

The Row address width in CSV file found in reference design is difference from K4A8G165WB datasheet.Refering to reference design，the capacity is not 8Gb but 4Gb.Is reference design wrong?

i must check, but prebuilt files was generated with this csv and they was running...see prebuilts
Xilinx has only this documentation and content has of the csv has changed form time to time, maybe there was some copy paste error from me.
https://support.xilinx.com/s/article/63462?language=en_US

I've holiday at the moment I can check this when I'm back.
br
John

[JH]

Hi,
can you tell me which datasheet you has used?
k4a8g165wb-birc is  8Gbit:
https://semiconductor.samsung.com/dram/ddr/ddr4/k4a8g165wb-birc/

And yes row address is wrong, should be 16 (but it works also with 15). We will change to 16 for 2021.2 release, which is in preparation at the moment. Thank you for pointing out this mistake.

br
John