Author Topic: CPLL in GTH Transceiver on TE0803 board not locking  (Read 444 times)


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CPLL in GTH Transceiver on TE0803 board not locking
« on: March 11, 2022, 02:16:24 PM »
Hi I'm having trouble implementing a GTH transceiver on a TE0803 SoM. The TE0803 has a Zynq Ultrascale+ ZU4CG on it, and I am using it with the TEBF0808 baseboard.

I have used the GT wizard in vivado to configure the GTH and generate an example design which I have then included in my block design. Initially I am trying to loopback the output serial data into the receiver, I am doing this by wiring the tx outputs of the example design to the rx inputs in the PL.

The design is using MGTREFCLK1 for reference and following the Trenz Starter Kit example and have configured the FSBL to program the SI5338 which drives this reference clock as required, the design is also using the CPLL rather than one of the QPLL. I believe the reference clock is working as I can detect activity on the GTREFCLK_MONITOR_OUT  port of the GTH when I enable it.

However when testing in hardware, when I release the GTH from reset, the CPLL appears to never lock. Though it appears to work fine when I simulate the example design.

I was initially using a reference frequency of 625MHz, I thought perhaps that the clock noise may be too high at this frequency which was causing the issue, however when i change the design and use a 125MHz reference clock is still fails to lock.

I am wondering if there are any required steps that I am missing? Or if anybody has had success with the GTH on the TE0803 and if so, using what frequencies and line rates? Are any steps required to enable the GT power supplies on the TE0803, i.e. MGTAVCC, MGTVCCAUX and MGTAVTT ?


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Re: CPLL in GTH Transceiver on TE0803 board not locking
« Reply #1 on: March 18, 2022, 08:20:05 AM »
Hi, GTH are enabled with TEBF0808 carrier and default CPLD Firmware.

As long as CPLL or QPLL not locked, you has a problem with reference CLK. TX RX loopback is no matter in this stage....maybe you has select wrong input or wrong frequency. Selected Reference CLK in this IP must match this one which is present on the selected CLK input pin. And this input clk freq. must be one of them which is be valid for GTH VCO. For Xilinx GTH mostly 125MHz(250MHz) or 156,25MHz(312,5MHz) will be used to support the most literates.