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errors in Vivado 2021.2 using 'preset.xml' file for TE0820

Started by dm1000, February 02, 2022, 05:34:39 PM

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dm1000

I get errors in Vivado "run block automation" when using the TE0820 board configuration.  These errors are for the processor block (zynq_ultra_ps_e).  When I remove 2 lines for the SD configuration in the 'preset.xml' file  - these
errors go away when running 'block automation'.  It looks like the BDF files are for an old version of the TE0820 Rev 3.  I have a Rev 4 version of the TE0820.  By removing these lines - I probably have disabled SD.   Does Trenz
have an updated TE0820 'preset.xml'  that works in Vivado 2021.2?

Here are the 2 errors in 'preset.xml'.  I tried many other different parameters with no success.  If I remove these 2 lines - I can proceed (synth,etc) with no errors.

        <user_parameter  name="CONFIG.PSU__SD0__PERIPHERAL__IO" value="MIO 13 .. 22"/>              <----- error  message is  [IP_Flow 19-3478] Validation failed for parameter 'SD0 IO(PSU__SD0__PERIPHERAL__IO)' with
value 'EMIO' for BD Cell 'zynq_ultra_ps_e_0'. PARAM PSU__SD0__PERIPHERAL__IO :: MIO 13 .. 22 is out of range { EMIO,MIO 13 .. 16 21 22,MIO 38 .. 44,MIO 64 .. 70 }

        <user_parameter  name="CONFIG.PSU__SD0__GRP_POW__IO" value="MIO 23"/>                            <------error message is [IP_Flow 19-3478] Validation failed for parameter 'POW IO(PSU__SD0__GRP_POW__IO)' with
value 'EMIO' for BD Cell 'zynq_ultra_ps_e_0'. PARAM PSU__SD0__GRP_POW__IO :: MIO 23 is out of range { EMIO }


JH

Hi,
download newest reference design(21.2):
https://wiki.trenz-electronic.de/display/PD/TE0820+Test+Board
board files are included. I could not detect an issue on my 2021.2
br
John

dm1000

I have a TE0820-04-2BE21FA.  Which board file do I use?
I am running Vivado v2021.2.1

./test_board/board_files (master) $ tree -L 2
.
├── TE0820_2CG_1E
│   ├── 1.0
│   └── 2.0
├── TE0820_2CG_1I
│   └── 2.0
├── TE0820_2EG_1E
│   ├── 1.0
│   └── 2.0
├── TE0820_2EG_1I
│   └── 2.0
├── TE0820_3CG_1E
│   ├── 1.0
│   └── 2.0
├── TE0820_3CG_1I
│   └── 2.0
├── TE0820_3EG_1E
│   ├── 1.0
│   └── 2.0
├── TE0820_4CG_1E
│   ├── 1.0
│   └── 2.0
├── TE0820_4CG_1I
│   └── 3.0
├── TE0820_4EG_1I
│   └── 2.0
├── TE0820_4EV_1E
│   └── 2.0
├── TE0820_4EV_1I
│   └── 2.0
├── TE0820_5EV_1I
│   └── 2.0
├── TE0820_5EV_1Q
│   └── 2.0
└── TE0820_board_files.csv

33 directories, 1 file

dm1000

Drilling down deeper into this folder - I see this tree.

/test_board/board_files (master) $ tree -L 24
.
├── TE0820_2CG_1E
│   ├── 1.0
│   │   ├── board.xml
│   │   ├── part0_pins.xml
│   │   ├── preset.xml
│   │   └── te0820_board.png
│   └── 2.0
│       ├── board.xml
│       ├── part0_pins.xml
│       ├── preset.xml
│       └── te0820_board.png
├── TE0820_2CG_1I
│   └── 2.0
│       ├── board.xml
│       ├── part0_pins.xml
│       ├── preset.xml
│       └── te0820_board.png
├── TE0820_2EG_1E
│   ├── 1.0
│   │   ├── board.xml
│   │   ├── part0_pins.xml
│   │   ├── preset.xml
│   │   └── te0820_board.png
│   └── 2.0
│       ├── board.xml
│       ├── part0_pins.xml
│       ├── preset.xml
│       └── te0820_board.png
├── TE0820_2EG_1I
│   └── 2.0
│       ├── board.xml
│       ├── part0_pins.xml
│       ├── preset.xml
│       └── te0820_board.png
├── TE0820_3CG_1E
│   ├── 1.0
│   │   ├── board.xml
│   │   ├── part0_pins.xml
│   │   ├── preset.xml
│   │   └── te0820_board.png
│   └── 2.0
│       ├── board.xml
│       ├── part0_pins.xml
│       ├── preset.xml
│       └── te0820_board.png
├── TE0820_3CG_1I
│   └── 2.0
│       ├── board.xml
│       ├── part0_pins.xml
│       ├── preset.xml
│       └── te0820_board.png
├── TE0820_3EG_1E
│   ├── 1.0
│   │   ├── board.xml
│   │   ├── part0_pins.xml
│   │   ├── preset.xml
│   │   └── te0820_board.png
│   └── 2.0
│       ├── board.xml
│       ├── part0_pins.xml
│       ├── preset.xml
│       └── te0820_board.png
├── TE0820_4CG_1E
│   ├── 1.0
│   │   ├── board.xml
│   │   ├── part0_pins.xml
│   │   ├── preset.xml
│   │   └── te0820_board.png
│   └── 2.0
│       ├── board.xml
│       ├── part0_pins.xml
│       ├── preset.xml
│       └── te0820_board.png
├── TE0820_4CG_1I
│   └── 3.0
│       ├── board.xml
│       ├── part0_pins.xml
│       ├── preset.xml
│       └── te0820_board.png
├── TE0820_4EG_1I
│   └── 2.0
│       ├── board.xml
│       ├── part0_pins.xml
│       ├── preset.xml
│       └── te0820_board.png
├── TE0820_4EV_1E
│   └── 2.0
│       ├── board.xml
│       ├── part0_pins.xml
│       ├── preset.xml
│       └── te0820_board.png
├── TE0820_4EV_1I
│   └── 2.0
│       ├── board.xml
│       ├── part0_pins.xml
│       ├── preset.xml
│       └── te0820_board.png
├── TE0820_5EV_1I
│   └── 2.0
│       ├── board.xml
│       ├── part0_pins.xml
│       ├── preset.xml
│       └── te0820_board.png
├── TE0820_5EV_1Q
│   └── 2.0
│       ├── board.xml
│       ├── part0_pins.xml
│       ├── preset.xml
│       └── te0820_board.png
└── TE0820_board_files.csv


But the problem configuration is the same in all of the above 'preset.xml' files. 

$ grep -r "CONFIG.PSU__SD0__PERIPHERAL__IO" ./
./TE0820_4EG_1I/2.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__PERIPHERAL__IO" value="MIO 13 .. 22"/>
./TE0820_2EG_1E/2.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__PERIPHERAL__IO" value="MIO 13 .. 22"/>
./TE0820_2EG_1E/1.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__PERIPHERAL__IO" value="MIO 13 .. 22"/>
./TE0820_4EV_1E/2.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__PERIPHERAL__IO" value="MIO 13 .. 22"/>
./TE0820_4CG_1E/2.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__PERIPHERAL__IO" value="MIO 13 .. 22"/>
./TE0820_4CG_1E/1.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__PERIPHERAL__IO" value="MIO 13 .. 22"/>
./TE0820_3EG_1E/2.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__PERIPHERAL__IO" value="MIO 13 .. 22"/>
./TE0820_3EG_1E/1.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__PERIPHERAL__IO" value="MIO 13 .. 22"/>
./TE0820_3CG_1E/2.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__PERIPHERAL__IO" value="MIO 13 .. 22"/>
./TE0820_3CG_1E/1.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__PERIPHERAL__IO" value="MIO 13 .. 22"/>
./TE0820_2EG_1I/2.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__PERIPHERAL__IO" value="MIO 13 .. 22"/>
./TE0820_2CG_1E/2.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__PERIPHERAL__IO" value="MIO 13 .. 22"/>
./TE0820_2CG_1E/1.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__PERIPHERAL__IO" value="MIO 13 .. 22"/>
./TE0820_5EV_1I/2.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__PERIPHERAL__IO" value="MIO 13 .. 22"/>
./TE0820_5EV_1Q/2.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__PERIPHERAL__IO" value="MIO 13 .. 22"/>
./TE0820_4EV_1I/2.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__PERIPHERAL__IO" value="MIO 13 .. 22"/>
./TE0820_4CG_1I/3.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__PERIPHERAL__IO" value="MIO 13 .. 22"/>
./TE0820_3CG_1I/2.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__PERIPHERAL__IO" value="MIO 13 .. 22"/>
./TE0820_2CG_1I/2.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__PERIPHERAL__IO" value="MIO 13 .. 22"/>

All files using the same value.

And grepping for the problem parameters in all of the 'preset.xml' files - I get

../TrenzRefDesign/test_board/board_files (master) $ grep -r "CONFIG.PSU__SD0__GRP_POW__IO" ./
./TE0820_4EG_1I/2.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__GRP_POW__IO" value="MIO 23"/>
./TE0820_2EG_1E/2.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__GRP_POW__IO" value="MIO 23"/>
./TE0820_2EG_1E/1.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__GRP_POW__IO" value="MIO 23"/>
./TE0820_4EV_1E/2.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__GRP_POW__IO" value="MIO 23"/>
./TE0820_4CG_1E/2.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__GRP_POW__IO" value="MIO 23"/>
./TE0820_4CG_1E/1.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__GRP_POW__IO" value="MIO 23"/>
./TE0820_3EG_1E/2.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__GRP_POW__IO" value="MIO 23"/>
./TE0820_3EG_1E/1.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__GRP_POW__IO" value="MIO 23"/>
./TE0820_3CG_1E/2.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__GRP_POW__IO" value="MIO 23"/>
./TE0820_3CG_1E/1.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__GRP_POW__IO" value="MIO 23"/>
./TE0820_2EG_1I/2.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__GRP_POW__IO" value="MIO 23"/>
./TE0820_2CG_1E/2.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__GRP_POW__IO" value="MIO 23"/>
./TE0820_2CG_1E/1.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__GRP_POW__IO" value="MIO 23"/>
./TE0820_5EV_1I/2.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__GRP_POW__IO" value="MIO 23"/>
./TE0820_5EV_1Q/2.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__GRP_POW__IO" value="MIO 23"/>
./TE0820_4EV_1I/2.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__GRP_POW__IO" value="MIO 23"/>
./TE0820_4CG_1I/3.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__GRP_POW__IO" value="MIO 23"/>
./TE0820_3CG_1I/2.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__GRP_POW__IO" value="MIO 23"/>
./TE0820_2CG_1I/2.0/preset.xml:        <user_parameter  name="CONFIG.PSU__SD0__GRP_POW__IO" value="MIO 23"/>


It looks like all the content in all of the above 'preset.xml' files are the same. 

JH

Hi,
you find correct files with "TE0820_board_files.csv"
TE0820-04-2BE21FA is te0820_2eg_1e --> 2.0

I've started it on my place without problem (see attachment).

Which OS did you use?
Did you create the Zynq IP and start directly board automation or did you change something on this IP (or open and close only) and start board automation later?
You can also create the project with our scripts, does this works?

br
John

dm1000

$ cat /etc/os-release
NAME="Ubuntu"
VERSION="20.04.3 LTS (Focal Fossa)"
ID=ubuntu
ID_LIKE=debian
PRETTY_NAME="Ubuntu 20.04.3 LTS"
VERSION_ID="20.04"
HOME_URL="https://www.ubuntu.com/"
SUPPORT_URL="https://help.ubuntu.com/"
BUG_REPORT_URL="https://bugs.launchpad.net/ubuntu/"
PRIVACY_POLICY_URL="https://www.ubuntu.com/legal/terms-and-policies/privacy-policy"
VERSION_CODENAME=focal
UBUNTU_CODENAME=focal


I made no changes in this IP core.

This should work in project mode with the GUI, right?

dave@Pulse15:~/.Xilinx/Vivado $ ls -l
total 24
drwxrwxr-x 11 dave dave 4096 Sep 15 15:20 2021.1
drwxrwxrwx 11 dave dave 4096 Jan 20 10:54 2021.2
drwxrwxr-x  4 dave dave 4096 Jan 24 21:03 2021.2.1
drwxrwxr-x  2 dave dave 4096 Sep 15 15:17 reportstrategies
drwxrwxr-x  2 dave dave 4096 Sep 15 15:17 strategies
drwxrwxr-x  2 dave dave 4096 Sep 15 15:17 tclapp

dave@Pulse15:~/.Xilinx/Vivado $ find ./ -name 'preset.xml'
./2021.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2021.1/boards/Trenz_Electronic/TE0820_2EG_1E/2.0/2.0/preset.xml
./2021.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2021.1/boards/Trenz_Electronic/TE0820_2EG_1E/1.0/1.0/preset.xml
./2021.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2021.1/boards/Trenz_Electronic/TE0820_2CG_1E/2.0/2.0/preset.xml
./2021.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2021.1/boards/Avnet/ultra96v2/1.1/1.1/preset.xml
dave@Pulse15:~/.Xilinx/Vivado $


There are no 'preset.xml' files in folder 2021.2.1.   But I am running Vivado v2021.2.1


JH

Hi,
there are different ways to install board file. Now you show Xilinx Board Store...you must download them with vivado before they are installed.  Or use local version, like I has suggested
Ways to install board files:
https://wiki.trenz-electronic.de/display/PD/Vivado+Board+Part+Flow

br
John

dm1000

See attachment.  This is the configuration I have after running 'block automation' with the 2 offending lines removed.

dm1000

I tried to follow your process on updating the board store.  FYI - the Vivado GUIs have changed.

I pointed to the v2021.2.1 repos and updated/refreshed.  But I still only have the old board files.   

dave@Pulse15:~/.Xilinx/Vivado $ find ./ -name 'preset.xml'
./2021.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2021.1/boards/Trenz_Electronic/TE0820_2EG_1E/2.0/2.0/preset.xml
./2021.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2021.1/boards/Trenz_Electronic/TE0820_2EG_1E/1.0/1.0/preset.xml
./2021.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2021.1/boards/Trenz_Electronic/TE0820_2CG_1E/2.0/2.0/preset.xml
./2021.1/xhub/board_store/xilinx_board_store/XilinxBoardStore/Vivado/2021.1/boards/Avnet/ultra96v2/1.1/1.1/preset.xml
dave@Pulse15:~/.Xilinx/Vivado $


And when I start a new project in Vivado - I can't add my TE0820 SOM.  See attachments.  The Finish button is grayed out.

So, I updated the board repos and it looks like this is not working in Vivado v2021.2.1

JH

Hi,
I've check it with my 2020.2 vivado. Open Board store, go to the TE0820 Variant, press right mouse button on the module and select install.  But something seems to be corrupted(I could not start the project).

I've removed local store folder and refresh Vivado store again. It doesn't help. I've tried the same with the board files from other vendor with the same results. Maybe something is corrupted on the whole store. I've waiting since December for updating master branch. https://github.com/Xilinx/XilinxBoardStore/pull/501
....

I would suggest you install these board files manually and use it from our reference design delivery:
https://wiki.trenz-electronic.de/display/PD/Vivado+Board+Part+Flow#VivadoBoardPartFlow-Option3:InstallintoaUserRepository

br
John

dm1000

After reading your last post - I was able to pull this Git repo

https://github.com/Xilinx/XilinxBoardStore.git

with success.  It was a Fast Forward merge (no merge conflicts). There is a lot of
recent activity.  Here is a snip of the Git log on the 'master' branch.

dave@Pulse15:~/FPGA/XilinxBoardStore/XilinxBoardStore (master) $ git log
commit 1729e2e232 (HEAD -> master, origin/master, origin/HEAD)
Author: xilinxgitops <xilinxgitops@xilinx.com>
Date:   Thu Feb 3 00:05:41 2022 -0700

    updated catalog file for PR#525

commit 9fe9a74b17
Merge: 51c0c844f5 98e0d3efc9
Author: xilinxgitops <xilinxgitops@xilinx.com>
Date:   Thu Feb 3 00:04:55 2022 -0700

    Merge commit '98e0d3efc901f0b974006bc4370c2a7ad8856c79'

commit 98e0d3efc9
Author: Siva Kemidi <53211271+shivakemidi@users.noreply.github.com>
Date:   Thu Feb 3 12:30:57 2022 +0530

    added new version for kv260 starter kit
   
    1.3(2022.1)
    Updated clock hierarchy

commit 51c0c844f5
Author: xilinxgitops <xilinxgitops@xilinx.com>
Date:   Wed Feb 2 23:39:38 2022 -0700

    updated catalog file for PR#524



However, it looks like the most recent update on the Trenz_Electronic folder is from date
11/14/2021.  Anyway, from my desk it appears that this Git repo is operating normally. 
I pulled the repo using Git from the command line - I did not use Vivado. There are a lot of
branches including a '2021.2' branch but I am assuming I should stay on 'master' branch for
the latest BDF files.  Assuming that everything is merged back into the 'master' branch.

None-the-less, I agree, the update utility for the board repos from inside Vivado looks to be a problem.  I could not
get it to work.  I guess I could use the XilinxBoardStore as a separate Git repo and just point to the files
inside Vivado?  Is that a good approach?  The user would have to remember to refresh (aka pull)
this repo to update. 

None-the-less, I think my original problem is due to Vivado.  As a work-around I can do the following.

a) delete the 2 offending lines in 'preset.xml' for the TE0820.
b) add the processor core to a block diagram (BD) in Vivado.
c) run block automation on this BD.  The result is no errors are reported by Vivado.
d) then modify the processor core to add back the correct SD configuraton that was removed from the 'preset.xml' file.

Then I find this commit from Xilinx in the Git repo.


commit 133be3ea61
Author: ashishd8 <ashishd@xilinx.com>
Date:   Tue Feb 1 21:18:38 2022 +0530

    Explicitly disabling SD0 interface for eMMC preset to fix CR-1115417


Digging deeper into the Git log - all the 'preset.xml' files were modified for the vck190 and vmk180.  This smells like a bug in Vivado.

When it comes to this kind of work - screen casts can be helpful.  I could make a screen cast of my workaround inside Vivado,
but I can't upload files like MP4 format to this forum.  Is there a way around this restriction - so I could share what I am doing in Vivado?
A short screen cast of a few minutes in duration could be helpful. 


JH

Hi,
CR-1115417 is interesting, I didn't heard this before. But until know I could not reproduce this issue on my side. Maybe it's a issue of the 21.2.1 patch from Vivado? Is there a reasion why you use the .1 patch? It's only need when you use:
    Zynq UltraScale+ MPSoCs: XCZU1CG, XCZU1EG
    Zynq UltraScale+ RFSoCs: XCZU42DR
See: https://support.xilinx.com/s/article/Vivado-2021-2-1-Release-Notes-and-Known-Issues?language=en_US

Regarding:
QuoteI guess I could use the XilinxBoardStore as a separate Git repo and just point to the files
inside Vivado?  I
It's easier to download our reference design:
https://wiki.trenz-electronic.de/display/PD/TE0820+Test+Board
and refer to the board_files folder of the reference design:
https://wiki.trenz-electronic.de/display/PD/Vivado+Board+Part+Flow#VivadoBoardPartFlow-Option3:InstallintoaUserRepository

br
John

dm1000

John

I am using the .1 patch because I was having problems with the IP packager in project mode.   One problem was, while editing some new IP, Vivado would close.
I was also experiencing some problems related to updating the IP.   

You have a PR 501 that is not complete on the XilinxBoardStore on GitHub.  It looks like this has been pending since last November.  It is not easier for me or more convenient to have to
download things like your reference design.  IMO, it is much more convenient to make a Git pull and update a repo - and do all of this from one location like the XilinxBoardStore
GitHub (one place to bookmark) then to remember to have to download and extract the Trenz reference design.  You can set alerts and watch for activity for any repo in GitHub.  I do not
see those type of utilities on your Trenz webpages.  GitHub is a very popular and useful Git hosting service - I think Trenz needs to make it a priority to support the XilinxBoardStore
repo. 

Back to my original post, the problem does not appear to be with the 'preset.xml' file.  The SD0 configuration has not changed from Trenz (either from the reference design or a repo).
The workaround is to follow the instructions in the Git commit message from Xilinx.  Explicitly disable the SD0 port pin assignments.  Then run 'block automation' in Vivado -  then reconfigure the SD0 port.

Lastly, I find it annoying for someone at Xilinx to post some mysterious number like CR-1115417 in a public Git repo.  I emailed the Xilinx person who posted this Git commit and kindly
requested more information.

JH

Hi,
QuoteGitHub is a very popular and useful Git hosting service - I think Trenz needs to make it a priority to support the XilinxBoardStore
repo. 
We will continue to use the github from xilinx, the problem is that there the maintenance takes much longer. Also, the board parts alone are not designed for modules, which usually simplifies the use with a reference design sometimes. And for SoC (Zynq,ZynqMP,RFSoC...) you has also related Software(FSBL, PMU...) which is related to the PS Configuration and this is still not available on this git....
I understand the reasons for your suggestion, I'll see what can be changed in the future.

QuoteBack to my original post, the problem does not appear to be with the 'preset.xml' file.  The SD0 configuration has not changed from Trenz (either from the reference design or a repo).
The workaround is to follow the instructions in the Git commit message from Xilinx.  Explicitly disable the SD0 port pin assignments.  Then run 'block automation' in Vivado -  then reconfigure the SD0 port.
. I use 2021.2 and can't still not reproduce this issue., maybe it's really related to the this .1 patch. But thanks for sharing this workaround.

QuoteLastly, I find it annoying for someone at Xilinx to post some mysterious number like CR-1115417 in a public Git repo.  I emailed the Xilinx person who posted this Git commit and kindly
requested more information.
If you get an answer it would be nice if you could share it here

br
John

dm1000

John

Is there anyway to post a short screencast in MP4?  Is there a Trenz email I could send it?

Yes, I will share if I hear anything back from Xilinx.  I have also asked an Avnet Xilinx FAE for some help - to see if he can chase down more info
related to CR-1115417.   

JH

Hi,
Quote
Is there anyway to post a short screencast in MP4?  Is there a Trenz email I could send it?
Support Email but it's not needed I believe you. I only say I can't reproduce this issue on my place. And I'm not a friend of videos.... ;-)
If you want that I should check something, start our reference designs with the provided scripts(https://wiki.trenz-electronic.de/display/PD/TE0820+Test+Board#TE0820TestBoard-DesignFlow) and send me one time the log file (it will be generated in the subfolder test_board/v_log/vivado.log).

br
John

JH

Hi,
CR-1115417  is only related to vck190/vmk180. Customer can't select SD because MIOs are overlaped with default USB interface, which prevent selection (option will not shown...or force some error depending on execution order...).
I know this problem, this can always happen not only  on SD interface...that's the question of how you want it. A long list where you can't choose anything but you get to know why or a short list with the remaining possibilities. Xilinx has chosen the second option. :-)

I think your problem is still related only on your PC.  I don't know why it happens there. Our project delivery is script based and you can create whole project by executing the our batch file. When you do this, scripts will write whole report to  test_board/v_log/vivado.log. When you send me this file, than I can check one time if I see some reason for this behaviour on your PC.
br
John