Author Topic: TE0726 - Bare minimum application  (Read 635 times)

Plotti

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TE0726 - Bare minimum application
« on: January 19, 2022, 10:06:07 AM »
Hi.

After 10 years of working with Intel/Altera FPGAs, I've recently switch to a new department using Xilinx Ulatrascale ZYNQs.
So I privately purchased a TE0726 board to understand the underlying basics of such platforms.

I created a bare minimum FPGA design in Vivado 2020.2 with just the 2 PS-UARTs connected to some output pins (with FTDI2232 and osci connected).
Then I created a Vitis "standalone" application using the "Hello World" Xilinx example. I can download this to the ZynqBerry and can step through the code using the debugger.

But if I try the official Xilinx UART Demos, which are displayed in the Board-Support-Package GUI as "Examples",  the whole platform behaves strangely:
The debugging resets in random places, XUartPs_LookupConfig doesn't report any configuration, ...

Does anybody know if it is possible to create "simple" bare metal applications, and can provide a link for an example project?
Or is it always recommended to use a petalinux OS?


JH

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Re: TE0726 - Bare minimum application
« Reply #1 on: January 19, 2022, 02:36:05 PM »
Hi,
our reference design includes simple Hello TE0726 baremetal design --> same like Xilinx hello world only in endless loop:
https://wiki.trenz-electronic.de/display/PD/TE0726+Test+Board


Note: PS configuration on Vivado PS IP (Configuration of the Processor part) on the block design (you can start with our reference design), exported XSA(HW Definition file for Vitis or petalinux) and generate FSBL(which is need when you boot from QSPI, when you program Zynq from Vitis, Vitis use xilinx generated script version of the FSBL to initialise Zynq with correct configuration before application will be load). Bitstream programming itself will not initilise PS(Processor part)
br
John
 

Plotti

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Re: TE0726 - Bare minimum application
« Reply #2 on: January 27, 2022, 10:42:09 PM »
Just in case somebody is googling the same issue:

Somehow I got mixed up with the 11 different versions of the TE0726, so I selected the wrong DDR Timings and DDR size in the Zynq configuration.
After selecting "MT41J256M16 RE-125" with low voltage (the last entry in the list) for my TE0726-03-41C64-A , each application is now working as intended. Now I hope I'll get my own petalinux up and running soon...

Best regards,
Dirk

JH

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Re: TE0726 - Bare minimum application
« Reply #3 on: January 28, 2022, 05:53:59 AM »
Hi,
I give you the full name of your TE0726, when you send the the serial number of the module (it's on the small sticker with QR code).

I know different assembly option makes it sometimes not easy to find the own configuration, but the lifetime of the Xilinx SoC is much bigger than on other components, so we must change it from time to time.

br
John