MIG Spartan6

[federigi]

Hello Rifo and those who can help me
 I'm trying to accomplish that Rifo has already done what I refer to 752x480 block in memory, reading and writing block. (Posts of 04/09/2011)
 I implemented the design in ISE 13.2 WebPack for LX45. (GigaBee TE600-45)
 I tried to generate the MIG, both with 3.61 than with 3.8, when I run my report generation error: ERROR: Pack: 2309 - Too many comps of type bonded "IOB" found to fit this device.
 I am baffled by this behavior  , you can help me?

 If you need my e-mail 3felettronica@3felettronica.com

 thanks

 Dino

[Ales Gorkic]

Dear federigi,

You are probably trying to implement the user_design from them MIG project.
Important to note is that user_design has open ports for connection to data interface (buses, handshaking). This one should be used ONLY if you have something connected to the MIG core - user design should drive this pins. If you do not connect anything the tools will connect them to free IOs with default volatage (LVCMOS25). When there are not enough free pins then you get the error you are describing.

If you just want to test the MIG core functionality then use example_design. This one has synthesizable testbench connected to MIG core. This testbench tests the memory and two status outputs:
calib_done
error     

Use this one for a start. When you know how the MIG core works you can make your own peripheral which connects to MIG signals in user_design.
Read the ug388.pdf for reference how to interface the MIG core.

Best regards,

Ales


 

[federigi]

Hello Ales
Thanks for your prompt response.
Dino

[federigi]

Hello Ales
 I am following your advice, but they are still struggling. In the past I used Spartan3 with excellent results, I always used the schematic to implement my plans.
 TE0600 Card:
 I tried to create a user and MIG Schematic hysteresis converted using the "Create Schematic Symbol" I then matched with the corresponding pin outputs the file. Ucf, I synth it all without errors.
 I downloaded the program to the FPGA, normally TE0603 light LED on the board if it works and even the LED lights on the TE0600 but with the MIG synth as mentioned above is all off.
 A simple 4-bit counter in the diagram included with the form MIG does not work anymore.
 Perhaps the MIG can not be converted into a block schematic?
 It 'can be integrated into a schematic block MIG without converting the schematic, if you do I do?
 There is a basic design which can then expand with customizations?
 I know I ask so much but I need to understand where I'm wrong.
 Thank you very much
 Dino

[Ales Gorkic]

Hi Dino,

Did you try to create schematic design without MIG core inside.
I suspect something different: unused pins are tied to GND, which can cause the FPGA to be kept in reset.
To fix this follow this steps:
open properties of Generate Programming File
under Configuration Options find -g: UnusedPin: select Float

I hope this helps.

Best regards,

Ales

[rifo]

Hello,

I haven't checked the forum for some time. Sorry for the late reply . I have updated the SVN gigabee-rifo trunk. Simulation in ISIM works okey. The design also synthesizes and place&routes fine. I haven't implemented the design on Gigabee and run a test on Gigabee. You can use the script* for both simulation and implementation.

feel free to make improvements/bug fixes
rifo

* Scripts are for linux platform.  For windows I guess one can copy isim.sh contents to isim.bat

[federigi]

Hello everyone
Question: Is there a concrete plan that implements the use of memory mounted on the cards "Gigabee"? Let me explain, I have tried, unsuccessfully, a guide to using the files generated by MIG, not the files to run the simulation, but the ones that should be used in the final project.
The Xilinx is not very clear on this subject, guides UG416 and 388 are not of great cars. After yet another failure, (I lost count of how many I have done ) I'm back to "Spartan3", which obviously is far from Spartan6 performance, but it works!!!!!
They are disoriented, in the initial project card "Gibabee" solved many functions, are now forced to review the draft with two "Spartan3" and a "Colrunner II."
I hope someone can help me, I would go back to using the "Gigabee".

Thanks
            Dino

[rifo]

Hello Dino,

Have you tried building the design in svn-rifo branch and run it on hardware? or before that have you reviewed the code? Can you tell me what's not working or things that does not make sense to you? A couple of additional points

1) I have done a limited simulation in ISIM and reads/writes to the DDR were working fine
2) The design builds fine. I have also modified the UCF file for Gigabee platform.

As far as I see, there is not a concrete plan for making use of DDR on Gigabee with MIG. Ales will certainly help us but you have to contribute too. Have you checked the code that Ales sent?

[federigi]

Hello everyone
The project I'm working on: To fetch a camera CCIR standard analog signal, the scan with an AD converter with a sampling rate 25 MHz digital signal enters the FPGA and also the sync signals. A 10-bit counter generates the addresses for memorize words in the memory relating to a line image, another counter  increase the memory address for successive scan lines, the videos synchronism synchronize the counters.
Son with other counters blanking signals. There are two memory that are activated alternately a read and a write, read and write to each picture are reversed.
I read a word from memory (refer to image previously stored) the processing and storage, but in the same location in memory that is in writing, this allows me to have all the time needed to process the data in memory along with data coming from the AD converter. The result of processing them to send two more memories that use of the first in the same way, the reading of the latter is different, which is complemented with the addresses are read if  want to invert the image upside down or left right, flip and mirror. The addresses are generated by a CPLD. With another new acquaintances in a control FPGA which stores images of interest and then go to catch up. I do all this with a Spartan II and a Spartan3 Colrunner (the Spartan II because it already used in the old project). I would like to use a Spartan6 should be able to do all the work. I'm stuck when I was not able to implement the control memory in my project.
I implemented the accessory functions, counters, windows, etc.. created the file downloaded programming of the FPGA in the same and so far so good, but when I insert the block created by MIG for the management of the FPGA is programmed memories and captures everything, whereas before I had the test signal output from the FPGA, with the implementation of the block memory management, I have no output signal from the FPGA itself. It seems that blocking MIG blocks throughout the FPGA.

For my convenience I use the schematic, descriptive language I am not very familiar.

Any suggestions? Thanks

Dino

[rifo]

I suggest you go step by step. Verify a single module first. I can't possibly help you about what's wrong on your module with such general description.

You have to ask specific questions. Also by descriptive language, do you mean VHDL or Verilog? If yes, then doing such a project with the schematic way will be very difficult.

[federigi]

Hello Rifo
 Descriptive language: I was referring just to VHDL and Verilog
 The tests carried out:
 1 - Open new progetoo, "contatore" schematic in ISE 13.2 inserted binary counter connected to an input where you connect a signal generator to simulate the clock outputs connected, ucf files, checked with oscilloscope actual division of the frequency of the clock-generator: 2,: 4,: 8, etc. ...
 2 - Generated MIG with IPCore 3.8 (also tried versions 3.6 and 3.61), a DDR3.
 3 - Added user files in the project counter, converted to MIG block schematic.
 4 - Posted MIG schematic, in the "contatore" with the binary counter, connected block mig with 100 MHz clock input, read and write inputs etc.. outputs and outputs signals to the DDR by the board for testing. Updated files .ucf
 5 - Generated files "contatore.bit" without error.
 6 - Downloaded file to the FPGA.
 7 - The binary counter no longer works. WHY '? The MIG does not generate any signal !!!

Tried same process with a Spartan3, Xess old card, no MIG, with rows of DDR memory management Xess, everything works regularly implemented other functions (I used ISE 9.1 on another computer on again because I do not have parallel port, which is necessary to program the Xess card) memory write and read images captured from video.
   Dino

[Antti Lukats]

Hi

FIRST (and LAST ADVICE): NEVER EVER TRY to use schematics.
I repeat, DO NOT USE schematics. If you can not deal with VHDL seek help.

Sorry for saying this, but at the end of the day you would need to learn VHDL no matter what (or get a new job).
------------------

NEXT: for any project you make, put an blinking LED sign of life counter into the project, make sure it still blinks
when your remaining circuitry is added or modified.

There are many, many things that can go wrong. It is not that hard to kill YEARS of your life struggling.

Trenz has provided working and tested reference designs.

Step 1:

Get the reference design with the DDR3 memory working. (no modifications)

Step 2: Add led blinker to the reference design (yes you may need to learn VHDL todo this)

Step 3: Proceed adding the features you need. Testing after each modification.

Antti

PS I have wasted my years fighting with FPGA's, more than one, plenty of years. I know.
Take my advice, get it working! You will be better engineer then. Good luck.

[federigi]

Hello Lukas
 Thanks for the advice
 I would like to point out, without arguing, that if Xilinx (Xilinx and not only) provides an alternative method to VHDL to program FPGAs, this method produces the same result for the project, as noted previously, the project is already functioning with the Spartan II and spartantan 3 and CPLDs (use these components for several years) would go to the logical evolution Spartan 6.
 Spartan6 works with the entire project except for the memory management with the MIG, I can guarantee to have carried out the checks with the appropriate tools, digital oscilloscope, signal generator, video generator, tester, video digitization of the signal chain, playback on the monitor and anything else needed. Of course, all prepared using the library of graphic symbols (flip-flops, adders, and, buffers, etc. ..) the provision by ISE.
 The use of the graphics library is most convenient for me, although in some cases I have used VHDL, but this is my problem. If the MiG back to graphic block with a problem should be the same Xilinx to put into question, I gather from the forums that are not just me having problems with the MIG and many complain about the lack of documentation provided by the use of the Xilinx MIG in real applications.
 Rephrase my request if anyone has a program, practice, and spartan6 that uses DDR3 memory with the MIG and is willing to make it known to the public, could publish it and all those who have visited (more than one hundred ) this topic on this forum thank you.

 PS I too have struggled for years with electronics since the early germanium transistors to get to the processors and the gorgeous FPGA and CPLD (I also studied some years ago, VHDL).

 Thanks again for your suggestions, I might have to revisit past studies.

Dino

[Antti Lukats]

Hi

to our best knowledge Trenz DOES provide a working DDR3 reference design.

And yes we know MIG is a "big piece of shit", thats why I suggested not to fiddle around with it but take the SAFE path
(I explained it step by step in my posting to you).

As of using schematics, one example: we got a request to look and consult a project manager for some start-up company. We found a that they had used Xilinx schematics. Because the engineer LIKED it. It was too late to save that company. The VC backed off, and wrote 2 MILLION EUR into direct losses.

I did play with P416 Ge transistor in 1966. What I said was from heart and I still believe the best advice possible. Do not experiment. Not with MIG, use your life for something better (to experiment with), with MIG do as it has to be done, go safe route. Take WORKING reference design, and proceed from there. Do not attempt to generate anything at your own with MIG if that is already done and verified by others.

as of my commentary, see you are saying: IT DOESNT WORK. But you don't specify the issue. What does not work?

1) If you take Trenz REF design and implement it 1:1 DOES IT WORK? Answer can be YES or NO.

if answer to the above is NO, then send direct email complaint to Trenz and do not complain here!

(Vendors are keen to fix issues if notified. But you should YIELL on forums only as last attempt if they do not listen to you)

if answer to above is YES, then congratulations you have working DDR3 demo!

before you ANYTHING else you must have answered the above question and you can only proceed if the answer is YES

now assuming the answer was YES, next question:

2) I had working DDR3 design, I added custom code XXX, now it doesn't work, please help me!

when asking 2, you must then explain in deep detail, WHAT you did to break the working design, then maybe somebody can help you also.

uuuu somebody,,,, uu help me with DDR3 and MIG!

This is what your postings look like! Who can help on that?

Spartan-6 is not that much faster than Spartan-3A, remember this is LOW COST family, with SLOW fabric.
So DDR3 on S-6 needs special care, this understood by all engineers.

If you hoped that changing the number from 3 to 6 made speed improvement of 2x then you are wrong.
It did not. And anyway the thing that MAKES FPGA's to work at all, is TIMING constraints. This is something
not all understand. FPGA is by itself a BAD AND SLOW SOMETHING, that is made to work as desired by the
magic of the mapper, fitter, router and TIMING tools. This is where the FPGA company know how is.
Not how to make silicon. But how to make the design work on SLOW silicon. The routing delays are
considerable, without black magic (timing driven routing, etc) nothing would work at all in modern FPGA's.

And yes, I have made a working design using manual DIE editor for XC2064 using all but 2 flip flops
available in that chip.

I am still hoping you take my advice and move the only reasonable path.

Antti