Inter-FPGA-Communication: write config flash of a second FGPA

[masc]

Dearl all!

I would like to throw a question in the room:

We are developing a system that needs inter-FPGA-communication. Think of a Zynq that exchanges data via SPI with two (or four) Artix.
During development time programming (FPGA and config flash) and debugging is done via JTAG chain.
But later in the field we would like to be able to still do updates. So we are looking for a possibility to program the artix config flash from the petalinux of the zynq.

See attached image.

What would be best practice to accomplish that?
-   Are there tools available for petalinux to write to the config flash via jtag? Without a "jtag programming cable" the jtag chain isn't closed... (jumper, but is it possible?)
-   Use a 2nd CS (e.g.CS_A`) that switches a mux inside the Artix and connects transparently the config flash of an artix to the zynq via SPI? (is QSPI a problem here?)
-   Anything else?

What do you think? Any ideas?

Any hint is gratefully welcome.
Thanks in advance, stay healthy. Bye, Marc.

P.S.: Oh, I just found the "Xilinx Virtual Cable": https://www.xilinx.com/support/documentation/application_notes/xapp1251-xvc-zynq-petalinux.pdf Can it be used to program the config flash without the need for a full Vivado installation?

[JH]

Hi,
xapp1215 is possible(Ive done it one time, with some modification of the xilinx example code). In this case you use a Zynq as programmer. But in this case you save only the programmer with Xilinx license. JTAG goes over ETH in this case and you see the connected device in Vivado (instead of full version, use free Vivado Labtools (much smaller->> ~1GB)).

br
John

[JS]

What about an easy streaming interface like token ring operating with serial interconnection? I built a master listener system with 8 clients and one controller this way, offering 50% of the slot time to the master and 50%/8 to the clients. The all need one pin only for IN and OUt = 2 Pins

In a maximum Test i ran it with 135MHz single ende using a b4b7 code. Practically this is close to 10Mbps for the Master to the clients and exceeds the formely used BMC b1b2 as S/PDIF.

For a professional system a LVDS = 4 wires would be the best.

[Trensica]

This configuration is capable of achieving a practical data rate close to 10Mbps from the master device to the clients. It is mentioned that this data rate exceeds the previously used BMC (b1b2) encoding commonly used in S/PDIF in S/PDIF (Sony/Philips Digital Interface) audio connections.

In the context of professional systems, it is suggested that a Low Voltage Differential Signaling (LVDS) implementation using 4 wires would be the optimal choice. LVDS is a signaling method that provides high-speed and noise-immune data transmission. It typically uses a differential pair of wires to transmit data and a separate pair for the complementary signal, resulting in a total of four wires.