I believe I have finally solved an intermittent reboot problem that has been vexing me for a few months. I am using the following products:
- SoM: TE0803-4BE11-A
- Carrier: TEBT0808
- I also have a custom board that closely follows the TEBT0808 design
- JTAG Adapter: TE0790-2
- DIP switch config:
- SW2-1 ON (CPLD not in update mode)
- SW2-2 OFF
- SW2-3 OFF (CPLD VIO sourced from J2-6, which is connected to PS_1V8 on the carrier)
- SW2-4 OFF (TE0790 powered from carrier board 3.3V via J2-5)
The intermittent reboots appear to stem from a marginal voltage on the master reset (MR) net.
On the TE0803, MR is connected to U41 (TI TPS3106K33DBVR) where it is internally pulled up to VDD (LP_DCDC, 3.3V).
On the TE0790, the "G" pin on the CPLD is used to drive MR. The TE0790 TRM states that pin G has an internal pull-up in the CPLD. This pull-up is to VIO, which needs to be 1.8V for this system config due to direct connection of the UART to the PS 1.8V bank.
This pull-up is fighting against the 3.3V pull-up in U41 on the TE0803.The minimum input high (V_IH,min) of the TPS3106K33DBVR is 0.7*Vdd. Vdd is connected to 3.3V, so the input needs to be kept above 2.31 V to avoid resets. On the units I have hear, MR tends to float around 1.9 V.
Does this analysis and conclusion seem correct?
My temporary workaround is to sever the connection to the TE0790 CPLD. The downside is that the reset button on the TE0790 is no longer usable.
It would be great if the CPLD firmware could be revised to disable the pull-up on pin G, but I'm not sure how that would impact other use cases for this product.
