Author Topic: vitis program FPGA trouble(TE0712 and TE0705 together.)  (Read 416 times)

gtfeel

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vitis program FPGA trouble(TE0712 and TE0705 together.)
« on: December 27, 2021, 05:51:40 AM »
hello.

I am using TE0712 and TE0705 together.
A problem occurred while using the sample provided by Trenz (vivado 2019.2)
Test the FreeRTOS lwip Echo Server provided by vitis. But the Program FPGA doesn't work.



The console error message is as follows.

cmd /C updatemem -force -meminfo \
D:/WORK/mocroblaze/SRC/TEST_LWIP6/3333/_ide/bitstream/msys_wrapper.mmi -bit \
D:/WORK/mocroblaze/SRC/TEST_LWIP6/3333/_ide/bitstream/msys_wrapper.bit -data \
D:\WORK\mocroblaze\trenz\test_board_20211221\firmware\microblaze_mcs_0\scu_te0712.elf \
-proc msys_microblaze_mcs_0_0/microblaze_I -out \
D:/WORK/mocroblaze/SRC/TEST_LWIP6/3333/_ide/bitstream/temp1.bit

****** updatemem v2019.2 (64-bit)
  **** SW Build 2708876 on Wed Nov  6 21:40:23 MST 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source D:/xilinx/Vitis/2019.2/scripts/updatemem/main.tcl -notrace
Command: update_mem -meminfo D:/WORK/mocroblaze/SRC/TEST_LWIP6/3333/_ide/bitstream/msys_wrapper.mmi -data {D:\WORK\mocroblaze\trenz\test_board_20211221\firmware\microblaze_mcs_0\scu_te0712.elf} -proc msys_microblaze_mcs_0_0/microblaze_I -bit D:/WORK/mocroblaze/SRC/TEST_LWIP6/3333/_ide/bitstream/msys_wrapper.bit -out D:/WORK/mocroblaze/SRC/TEST_LWIP6/3333/_ide/bitstream/temp1.bit -force
0 Infos, 0 Warnings, 0 Critical Warnings and 1 Errors encountered.
update_mem failed
ERROR: [Updatemem 57-85] Invalid processor specification of: msys_microblaze_mcs_0_0/microblaze_I. The known processors are: msys_i/microblaze_0 msys_i/microblaze_mcs_0/U0/microblaze_I

INFO: [Common 17-206] Exiting updatemem at Mon Dec 27 13:26:02 2021...

cmd /C updatemem -force -meminfo \
D:/WORK/mocroblaze/SRC/TEST_LWIP6/3333/_ide/bitstream/msys_wrapper.mmi -bit \
D:/WORK/mocroblaze/SRC/TEST_LWIP6/3333/_ide/bitstream/temp1.bit -data \
D:\WORK\mocroblaze\SRC\TEST_LWIP6\3333\Debug\3333.elf -proc msys_i/microblaze_0 -out \
D:/WORK/mocroblaze/SRC/TEST_LWIP6/3333/_ide/bitstream/download.bit
File D:/WORK/mocroblaze/SRC/TEST_LWIP6/3333/_ide/bitstream/temp1.bit does not exist

Usage: updatemem [options]
(Switches with double dash '--' can also be used with a single dash '-')

Help message:

  -h [ --help ]          Display help
  --meminfo arg          Input meminfo file with extension '.mmi' or .smi (for
                         generating .mem files). The .mmi file can be generated
                         using the write_mem_info TCL command in Vivado. The
                         Tcl generate_mem_files will generate the .smi file.
  --data arg             Input elf or mem file to be used to populate the
                         BRAMs. When writing .mem files for simulation this
                         command line argument will only accept elf input file
                         type.
  --bit arg              Input bit file
  --proc arg             Instance path of the processor in the design
  --out arg              Output bit file
  --force [=arg(=1)]     Overwrite existing output bit file

Examples:
  updatemem -meminfo top.mmi -data top.elf -bit top.bit -proc system_i/microblaze -out top_out.bit
  updatemem -meminfo top.mmi -data top.mem -bit top.bit -proc system_i/microblaze -out top_out.bit
  updatemem -meminfo top.mmi -data top.elf -bit top.bit -proc system_i/microblaze -out top_out.bit -force
Write out the translated elf file as a .mem file(s) for third party simulators.
  updatemem -meminfo top.smi -data top.elf -proc system_i/microblaze

cmd /C rm D:/WORK/mocroblaze/SRC/TEST_LWIP6/3333/_ide/bitstream/temp1.bit
rm: cannot remove `D:/WORK/mocroblaze/SRC/TEST_LWIP6/3333/_ide/bitstream/temp1.bit': No such file or directory




There seems to be a problem in the process of merging each .elf programmed in two mocroblaze.(microblaze_0, microblaze_mcs)
please tell me the solution

JH

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Re: vitis program FPGA trouble(TE0712 and TE0705 together.)
« Reply #1 on: January 03, 2022, 08:10:29 AM »
Hi,
Quote
rm: cannot remove `D:/WORK/mocroblaze/SRC/TEST_LWIP6/3333/_ide/bitstream/temp1.bit': No such file or directory
Did you checked if this bitstream exists?

Quote
There seems to be a problem in the process of merging each .elf programmed in two mocroblaze.(microblaze_0, microblaze_mcs)
No. this always depends on your BPS selection for the application (different mmi files will be generated which defines blockram which is used for the processor systems).
We add mcs  firmware elf and application elf directly in vivado(you can specify application there). Vitis should be also possible

PS: You can generate one for mcs and one for the normal microblaze. in case you wan't reconfigure SI5338, you can also create a design with only one microblaze.

br
John