Test MIG Spartan6

[federigi]

Friends of the Forum
I'm back to ask for help and your opinion.
I'm trying to work with the platform spartan6 GigaBee board the problem in the use of memory with the MIB.
Using a design ISE 13.2, GigaBee XC6Lx45 and a carrier board XC6SLX.
I implemented the MIG with IP Core for testing, as suggested by Xilinx (UG416 and UG 388) resulting in the folder "example_design" and "user_design".
Synthesis the "example_design" open "Chipscope Pro", but that does not want to be able to work, I try with "ISIM Simulator" Both start, set the clock displays the clock and sub clock, but the remaining signals are static, however the simulation does not help me much, I actually run a test on the card.
I tried to use the MIG with the AXI option, nothing has changed for the test.
When I download the program to the board on the carrier board LEDs light up the LED on the LX45 and also to show that everything should work (in a previous test with a simple counter that divides the clock, everything works fine)
Test_1: MIG with optional AXI, synthesis OK, convert it into a schematic diagram to add the test of the divider, natural to combine the outputs of the block with the pins of the schematic file "ucf" drain on the board, the LEDs light up the divisor function, MIG?
Test_2: use the "user_design". The summary does not go through.

ERROR: ConstraintSystem: 58 - Constraint <NET
"memc_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;> [ipcore_dir / Edk_mig_dino / user_design / par / Edk_mig_dino.ucf (38)]: NET
"MEMC? _wrapper_inst / Mcb_ui_top_inst / mcb_raw_wrapper_inst / selfrefresh_mcb_mode
"Does not match any design objects.

ERROR: ConstraintSystem: 58 - Constraint <NET "c?_pll_lock" TIG;>
[Ipcore_dir / Edk_mig_dino / user_design / par / Edk_mig_dino.ucf (39)]: NET
"C? _pll_lock" Does not match any design objects.

ERROR: ConstraintSystem: 58 - Constraint <INST
TIG;> [ipcore_dir / Edk_mig_dino / user_design / par / Edk_mig_dino.ucf (40)]: INST
"MEMC? _wrapper_inst / Mcb_ui_top_inst / mcb_raw_wrapper_inst / gen_term_calib.mcb_s
oft_calibration_top_inst / mcb_soft_calibration_inst / * DONE_SOFTANDHARD_CAL "
does not match any design objects.

The file "ucf"
.
.
################################################## ################################
# Ignore timing constraints for paths crossing the clock domain
################################################## ################################
NET "memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "c?_pll_lock" TIG;
INST "memc_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;.
.
.
The summary "example_design" these errors are not there, why?

If you comment out the line above I can sum up everything, but then the planning board fails. ??
I wrote the program in VHDL, when I can install on-board LEDs do not light and the meter does not work.

I think Trenz has performed all tests on the board, you can have the files used by laboratories for testing?
I also tried ALDESI files with the same results.
I am very perplexed and discouraged, I'm thinking of abandoning this platform because I have to find a solution soon.
Confident that I can to help, I thank you in advance.

Dino

[Ales Gorkic]

Hi Dino,

This MIG project was used to generate pinout for SDRAM for initial GigaBee board.
I have now opened it and checked how it is made.
The MIG tool now does not generate the clocks properly. When you make a Spartan6 MIG core with Coregen there is not specified what is the PLL input clock frequency.
This has to be edited manually in example_top.vhd if you use example design:
   constant Cx_CLKFBOUT_MULT        : integer := 16; --SET to 125MHz input clock
   constant Cx_DIVCLK_DIVIDE        : integer := 3;  --SET to 125MHz input clock
This way the MCB is clocked to 125*16/3 = 666MHz. The infrastructure_inst synthesizes the necessary clocks.
The input clock is differential by default and should be set to single ended (top generics):
   Cx_INPUT_CLK_TYPE       : string := "SINGLE_ENDED";
This should be done for both MCBs (x = 1 and 3).

The input clock for is also separate for each MCB. This should also be set to use only one clock source from LOC = "AA12", which has 125MHz frequency.
The clock buffers from the infrastructure core needs to be moved to top module to be able to drive both PLLs with the same input clock.

I have done all the necessary modifications to the files on the SVN, for example_design as well to the user_design.

Please not that to sucessfully implement the user design you need to set the ISE:
synthesis properties->Xilinx specific options->-iobuf (Add IO buffers) UNCHECKED
implement properties->map properties->-u (Trim unconnected signals) UNCHECKED
THIS WILL FORCE THE TOOLS TO MAP THE DESIGN INSIDE FPGA WITHOUT CONNECTING THE FREE SIGNALS TO IO PADS OR REMOVING THE UNCONNECTED LOGIC.
THIS APPLIES TO ALL PROJECTS WITH FREE SIGNALS!!


Best regards,

Ales

[federigi]

Hello Ales
You wrote "This has to be edited manually if you use example_top.vhd in the example design:
Cx_CLKFBOUT_MULT constant: integer: = 16; - SET input clock to 125MHz
   Cx_DIVCLK_DIVIDE constant: integer: = 3; - SET to 125MHz input clock "

                                                                       VHDL
example_top.vhd my file is:

- Device: Spartan-6
- Design Name: DDR/DDR2/DDR3/LPDDR
- Purpose: This is the top level design. Which wrapper instantiates the top,
- Infrastructure and bench top testing modules.
- Reference:
- Revision History:
--************************************************ *****************************
library ieee;
use ieee.std_logic_1164.all;
entity is example_top
generic
  (
            C3_P0_MASK_SIZE: integer: = 4;
          C3_P0_DATA_PORT_SIZE: integer: = 32;
          C3_P1_MASK_SIZE: integer: = 4;
          C3_P1_DATA_PORT_SIZE: integer: = 32;
    C3_MEMCLK_PERIOD: integer: = 2500;
                                       -- Memory data transfer clock period.
    C3_RST_ACT_LOW: integer: = 0;
                                       -- # = 1 for active low reset
                                       -- # = 0 for active high reset.
    C3_INPUT_CLK_TYPE: string: = "SINGLE_ENDED";
                                       -- Input clock type or SINGLE_ENDED DIFFERENTIAL.
    C3_CALIB_SOFT_IP: string: = "TRUE";
                                       -- # = TRUE Enables the soft calibration logic,
                                       -- # = FALSE Disables the soft calibration logic.
    C3_SIMULATION: string: = "FALSE";
                                       -- # = TRUE, Simulating the design. Useful to reduce the simulation time,
                                       -- # = FALSE, Implementing the design.
    C3_HW_TESTING: string: = "FALSE";
                                       -- Determines the address space accessed by the traffic generator,
                                       -- # = FALSE, Smaller address space,
                                       -- # = TRUE, Large address space.
    DEBUG_EN: integer: = 0;
                                       -- # = 1, Enable debugging signals / controls,
                                       -- = 0, Disable debugging signals / controls.
    C3_MEM_ADDR_ORDER: string: = "BANK_ROW_COLUMN";
                                       -- The Order In Which user is provided to address the memory controller,
                                       -- ROW_BANK_COLUMN BANK_ROW_COLUMN ago.
    C3_NUM_DQ_PINS: integer: = 16;
                                       -- External memory data width.
    C3_MEM_ADDR_WIDTH: integer: = 13;
                                       -- External memory address width.
    C3_MEM_BANKADDR_WIDTH: integer: = 3
                                       -- External memory bank address width.
  );

                                                                       Verilog
This is in "example_top.v"                 
//************************************************ *****************************
/ / ____ ____
/ / / / \ / /
/ / /___/ \ / Vendor: Xilinx
/ / \ \ \ / Version: 3.8
/ / \ \ Application: MIG
/ / / / Filename: # example_top. V
/ / /___/ / \ Date Last Modified: $ Date: 27/05/2011 15:50:38 $
/ / \ \ / \ Date Created: Fri Feb 23 2010
/ / \ ___ \ / \ ___ \
/ /
/ / Device: Spartan-6
/ / Design Name: DDR/DDR2/DDR3/LPDDR
/ / Purpose: This is a template file for the top design module. This module contains
/ / All the four memory controllers and the two Infrastructures. However,
/ / Only the enabled modules will be active and others inactive.
/ / Reference:
/ / Revision History:
//************************************************ *****************************
`Timescale 1ns/1ps

(* = X_CORE_INFO "mig_v3_8_ddr3_s6, Coregen 13.2", CORE_GENERATION_INFO = "ddr3_s6, mig_v3_8, component_name = {IPcore_Mig_Dino_1, C3_MEM_INTERFACE_TYPE = DDR3_SDRAM, C3_CLK_PERIOD = 2500, = C3_MEMORY_PART mt41j64m16xx-15th, C3_MEMORY_DEVICE_WIDTH = 16, = C3_OUTPUT_DRV DIV6, C3_RTT_NOM = DIV4, C3_AUTO_SR = ENABLED, C3_HIGH_TEMP_SR = NORMAL, C3_PORT_CONFIG = Two 32-bit bi-directional and four 32-bit unidirectional ports, C3_MEM_ADDR_ORDER = BANK_ROW_COLUMN, C3_PORT_ENABLE Port2_Port3 =, = C3_INPUT_PIN_TERMINATION CALIB_TERM, C3_DATA_TERMINATION = 25 Ohms, C3_CLKFBOUT_MULT_F = 2, C3_CLKOUT_DIVIDE = 1, C3_DEBUG_PORT = 0, INPUT_CLK_TYPE = Single-Ended, LANGUAGE = Verilog, SYNTHESIS_TOOL = Foundation_ISE, NO_OF_CONTROLLERS = 1} "*)
# module example_top
(
   C3_P0_MASK_SIZE parameter = 4,
   C3_P0_DATA_PORT_SIZE parameter = 32,
   C3_P1_MASK_SIZE parameter = 4,
   C3_P1_DATA_PORT_SIZE parameter = 32,
   DEBUG_EN parameter = 0,
                                       / / # = 1, Enable debugging signals / controls,
                                       / / = 0, Disable debugging signals / controls.
   parameter C3_MEMCLK_PERIOD = 2500,
                                       / / Memory data transfer clock period
   C3_CALIB_SOFT_IP parameter = "TRUE"
                                       / / # = TRUE Enables the soft calibration logic,
                                       / / # = FALSE Disables the soft calibration logic.
   C3_SIMULATION parameter = "FALSE"
                                       / / # = TRUE, Simulating the design. Useful to reduce the simulation time,
                                       / / # = FALSE, Implementing the design.
   C3_HW_TESTING parameter = "FALSE"
                                       / / Determines the address space accessed by the traffic generator,
                                       / / # = FALSE, Smaller address space,
                                       / / # = TRUE, Large address space.
   C3_RST_ACT_LOW parameter = 0,
                                       / / # = 1 for active low reset
                                       / / # = 0 for active high reset.
   C3_INPUT_CLK_TYPE parameter = "SINGLE_ENDED"
                                       / / Input or clock type DIFFERENTIAL SINGLE_ENDED
   C3_MEM_ADDR_ORDER parameter = "BANK_ROW_COLUMN"
                                       / / The Order In Which user is provided to address the memory controller,
                                       / / Or ROW_BANK_COLUMN BANK_ROW_COLUMN
   C3_NUM_DQ_PINS parameter = 16,
                                       / / External memory data width
   C3_MEM_ADDR_WIDTH parameter = 13,
                                       / / External memory address width
   C3_MEM_BANKADDR_WIDTH parameter = 3
                                       / / External memory bank address width
)

Which one is correct?

I am even more confused.

Dino

[Ales Gorkic]

Hi Dino,

These constants are in the middle of the file.
Simply search for:
C1_CLKFBOUT_MULT
And
C3_CLKFBOUT_MULT

One for each PLL instance in the infrastructure core.

Best regards,

Ales

[federigi]

Hello Ales
I'm sorry for this oversight.
I created again the MIG.
The simulation "ISIM" okay.
As for changing the clock frequency error for me exceeded 1050MHz, but that, at present, is not a problem.
Now that I have all the files in the folder where I created the MIG (example_design and user_design) I put the files in my project of MIG, schematic, where there are blocks that generate the addresses and send data to memory.
Can you give me some suggestions?
thanks
     Dino

[Ales Gorkic]

Hi Dino and also a tip to others who are using PLLs,

These max/min PLL frequency problems can be a nighmare.
When calculating the PLL parameters I do the following:
add new file to project
select IP core generator file
from available cores select Clocking Wizard

At coregen window:
Select Manual selection then select PLL_BASE
fill the Input Frequency (125MHz in my case)
then in next window fill the desired frequencies (CLOCK_OUT1 and 2  are 666MHz for MCB, others are user clocks in MIG design)
and voila at the last window you get all the desired parameters.
If the frequency you selected is impossible to synthesize the Coregen will tell you and also tells you which buffer can be used for the desired frequency.

Best regards,

Ales