Vivado synth error due to two IP cores having submodules with the same name

[Stonebull]

Hello!
I am using Vivado 2019.1 and I am experiencing problems with two IP cores that I wrote and packaged with the IP packager and instantiated in the same block design.
The two Ip cores casually have got sub modules that have the same file name and entity name. This apparently leads to Vivado complaining:

[filemgmt 20-1741] File 'debounce.vhd' is used by one or more modules, but with different contents, and may lead to unpredictable results:
* zsys_I2C_Filter_0_0 (e:/MyDesign.srcs/sources_1/bd/zsys/ipshared/3b6f/sources_1/imports/Downloads/debounce.vhd)
* zsys_AxiGpioMuxVhdl_0_0 (e:/MyDesign.srcs/sources_1/bd/zsys/ipshared/915a/hdl/debounce.vhd)
Please reset and regenerate these modules to resolve the differences, or synthesize them independently.

Is this really a problem for Vivado, if IP cores use sub modules that have the same name? This could potentially be happening all the time then in a block design that uses many IP cores.
How can I resolve this issue, preferably withought having to change the file or entity name of the modules?

The error message suggests to "synthesize them independently" how can I do that, and still use them in the same block design?


Thanks a lot for your help!

[Stonebull]

Apparently you have to Generate the Output Products Out-Of-Context (OOC) to solve this.

[JH]

Hi,

thank you to post also a solution for your problem.

This problem you has is a Vivado tool problem, it's normally better to post such issues on the Xilinx forum. Xilinx community is much bigger and Xilinx maybe recognise that they have problems with there tools and can fix it.

In case you has problems with the trenz module itself than it make more sense to use this forum.

br
John

[Stonebull]

Thanks for your reply. I did post this problem and several others on the Xilinx Forum. The problem is I rarely get a response there. Therefore I tried it here as well.

[JH]

Hi,

The problem is I rarely get a response there

I know, it depends always on the content. But the chance that someone can help is still greater there with such problems.
I use default OOC, it will save translation/syntheses time. So I didn't recognised this issue until now.

Maybe it's one of the know issues from Xilinx and it is fixed on a newer version.
I've created links to the Xilinx documentation for the different versions (we use mostly even vivado versions):
https://wiki.trenz-electronic.de/display/PD/Xilinx+Development+Tools#XilinxDevelopmentTools-XilinxSoftware-ProductUpdateReleaseNotesandKnownIssues

Sometimes it makes sense to check if you find your issue in such a list from Xilinx.

br
John

[JH]

Hi,
maybe check:
https://support.xilinx.com/s/global-search/%5Bfilemgmt%2020-1741%5D%20File?language=en_US
--> https://support.xilinx.com/s/question/0D52E00006hpbQxSAI/filemgmt-201741-with-custom-ip-file-used-by-one-or-more-modules-but-with-different-contents?language=en_US
--> https://support.xilinx.com/s/question/0D52E00006hpQFDSA2/regslicecorev-from-different-hls-versions-results-in-filemgmt-201741-critical-warning-with-global-synthesis?language=en_US

it looks like they have a similar problem(I didn't read the whole posts), so I don't know if they found other solutions to fix this problem.

br
John

[Stonebull]

Thanks for your suggestions.

I have searched through the Xilinx forum previously to post my question but apparently I was not rigorouse enough.


@JH
I know that this still is not the correct place to ask and totally unrelated by the way, but as we are already in a conversation I would like to ask you if you know a possibility to pass parameters from your custom IP core to the software driver. I'm thinking of an automatically generated #define that appears in the xparameters.h include upon BSP generation.
Something like this define generated by the QSPI AXI Core:

#define XPAR_XQSPIPS_0_QSPI_MODE 0

Maybe you have already used this features in your cores somewhere and can give me a quick hint how to do it or where to find information.

Best Regards,

[JH]

Hi,
I would suggest you use Xilinx IP Wizard and you select new AXI4-Periherial. In this case you has standard defines to use it in Vitis and petalinux:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug1118-vivado-creating-packaging-custom-ip.pdf
page 30ff

it looks like 20.1 has a bug, so use other Vivado version:
https://support.xilinx.com/s/article/75655?language=en_US

Xilinx information about special features are mostly rare, often it helps when you check Xilinx IPs itself (C:\Xilinx\Vivado\<Vivado Version>\data\ip) to get such information.

br
John