Hello Ales
You wrote "This has to be edited manually if you use example_top.vhd in the example design:
Cx_CLKFBOUT_MULT constant: integer: = 16; - SET input clock to 125MHz
Cx_DIVCLK_DIVIDE constant: integer: = 3; - SET to 125MHz input clock " VHDL
example_top.vhd my file is:
- Device: Spartan-6
- Design Name: DDR/DDR2/DDR3/LPDDR
- Purpose: This is the top level design. Which wrapper instantiates the top,
- Infrastructure and bench top testing modules.
- Reference:
- Revision History:
--************************************************ *****************************
library ieee;
use ieee.std_logic_1164.all;
entity is example_top
generic
(
C3_P0_MASK_SIZE: integer: = 4;
C3_P0_DATA_PORT_SIZE: integer: = 32;
C3_P1_MASK_SIZE: integer: = 4;
C3_P1_DATA_PORT_SIZE: integer: = 32;
C3_MEMCLK_PERIOD: integer: = 2500;
-- Memory data transfer clock period.
C3_RST_ACT_LOW: integer: = 0;
-- # = 1 for active low reset
-- # = 0 for active high reset.
C3_INPUT_CLK_TYPE: string: = "SINGLE_ENDED";
-- Input clock type or SINGLE_ENDED DIFFERENTIAL.
C3_CALIB_SOFT_IP: string: = "TRUE";
-- # = TRUE Enables the soft calibration logic,
-- # = FALSE Disables the soft calibration logic.
C3_SIMULATION: string: = "FALSE";
-- # = TRUE, Simulating the design. Useful to reduce the simulation time,
-- # = FALSE, Implementing the design.
C3_HW_TESTING: string: = "FALSE";
-- Determines the address space accessed by the traffic generator,
-- # = FALSE, Smaller address space,
-- # = TRUE, Large address space.
DEBUG_EN: integer: = 0;
-- # = 1, Enable debugging signals / controls,
-- = 0, Disable debugging signals / controls.
C3_MEM_ADDR_ORDER: string: = "BANK_ROW_COLUMN";
-- The Order In Which user is provided to address the memory controller,
-- ROW_BANK_COLUMN BANK_ROW_COLUMN ago.
C3_NUM_DQ_PINS: integer: = 16;
-- External memory data width.
C3_MEM_ADDR_WIDTH: integer: = 13;
-- External memory address width.
C3_MEM_BANKADDR_WIDTH: integer: = 3
-- External memory bank address width.
);
Verilog
This is in "
example_top.v"
//************************************************ *****************************
/ / ____ ____
/ / / / \ / /
/ / /___/ \ / Vendor: Xilinx
/ / \ \ \ / Version: 3.8
/ / \ \ Application: MIG
/ / / / Filename: # example_top. V
/ / /___/ / \ Date Last Modified: $ Date: 27/05/2011 15:50:38 $
/ / \ \ / \ Date Created: Fri Feb 23 2010
/ / \ ___ \ / \ ___ \
/ /
/ / Device: Spartan-6
/ / Design Name: DDR/DDR2/DDR3/LPDDR
/ / Purpose: This is a template file for the top design module. This module contains
/ / All the four memory controllers and the two Infrastructures. However,
/ / Only the enabled modules will be active and others inactive.
/ / Reference:
/ / Revision History:
//************************************************ *****************************
`Timescale 1ns/1ps
(* = X_CORE_INFO "mig_v3_8_ddr3_s6, Coregen 13.2", CORE_GENERATION_INFO = "ddr3_s6, mig_v3_8, component_name = {IPcore_Mig_Dino_1, C3_MEM_INTERFACE_TYPE = DDR3_SDRAM, C3_CLK_PERIOD = 2500, = C3_MEMORY_PART mt41j64m16xx-15th, C3_MEMORY_DEVICE_WIDTH = 16, = C3_OUTPUT_DRV DIV6, C3_RTT_NOM = DIV4, C3_AUTO_SR = ENABLED, C3_HIGH_TEMP_SR = NORMAL, C3_PORT_CONFIG = Two 32-bit bi-directional and four 32-bit unidirectional ports, C3_MEM_ADDR_ORDER = BANK_ROW_COLUMN, C3_PORT_ENABLE Port2_Port3 =, = C3_INPUT_PIN_TERMINATION CALIB_TERM, C3_DATA_TERMINATION = 25 Ohms, C3_CLKFBOUT_MULT_F = 2, C3_CLKOUT_DIVIDE = 1, C3_DEBUG_PORT = 0, INPUT_CLK_TYPE = Single-Ended, LANGUAGE = Verilog, SYNTHESIS_TOOL = Foundation_ISE, NO_OF_CONTROLLERS = 1} "*)
# module example_top
(
C3_P0_MASK_SIZE parameter = 4,
C3_P0_DATA_PORT_SIZE parameter = 32,
C3_P1_MASK_SIZE parameter = 4,
C3_P1_DATA_PORT_SIZE parameter = 32,
DEBUG_EN parameter = 0,
/ / # = 1, Enable debugging signals / controls,
/ / = 0, Disable debugging signals / controls.
parameter C3_MEMCLK_PERIOD = 2500,
/ / Memory data transfer clock period
C3_CALIB_SOFT_IP parameter = "TRUE"
/ / # = TRUE Enables the soft calibration logic,
/ / # = FALSE Disables the soft calibration logic.
C3_SIMULATION parameter = "FALSE"
/ / # = TRUE, Simulating the design. Useful to reduce the simulation time,
/ / # = FALSE, Implementing the design.
C3_HW_TESTING parameter = "FALSE"
/ / Determines the address space accessed by the traffic generator,
/ / # = FALSE, Smaller address space,
/ / # = TRUE, Large address space.
C3_RST_ACT_LOW parameter = 0,
/ / # = 1 for active low reset
/ / # = 0 for active high reset.
C3_INPUT_CLK_TYPE parameter = "SINGLE_ENDED"
/ / Input or clock type DIFFERENTIAL SINGLE_ENDED
C3_MEM_ADDR_ORDER parameter = "BANK_ROW_COLUMN"
/ / The Order In Which user is provided to address the memory controller,
/ / Or ROW_BANK_COLUMN BANK_ROW_COLUMN
C3_NUM_DQ_PINS parameter = 16,
/ / External memory data width
C3_MEM_ADDR_WIDTH parameter = 13,
/ / External memory address width
C3_MEM_BANKADDR_WIDTH parameter = 3
/ / External memory bank address width
)
Which one is correct?
I am even more confused.
Dino
