micro-SD card (LVS) "direct connection" at 1.8V signal levels possible?

[jconradt]

Hi Trenz community,

in our development setup, we use a TE0715-04-15-1I on a TE0701 Carrier Board, which boots PetaLinux from a micro SD card. Everything works fine.

For the final system we want to reduce components and we plan to directly drive the µSD card from FPGA signals, instead of going through a level shifter as on the Trenz Carrier board (1.8V <-> 3.3V, TXS02612). Our test board with direct SDIO signal connections does not boot reliably. Sometimes we get the first boot message, sometimes a bit "more"; sometimes not even the first bootup. Below the "most successfull" boot log, which clearly shows that the problem is a µSD card IO error.

Using the same µSD card in the Trenz Carrier Board (TE0701, with level shifter) works consistently. We have tried several different µSD cards, all of which are "A2 specified" (A2 includes LVS, so they should work at "only" 1.8V signal level). The µSD cards are powered at 3.3V, only the signalling is direct from the FPGA, and therefore at 1.8V level.

Has anyone booted PetaLinux from µSD cards at 1.8V signal levels?

We read about an initialization sequence that the µSD-card needs to switch to 1.8V, but we could not find any technical details. Where would such a sequence be issued?


Thanks for any suggestions!

Jörg

=====

Xilinx First Stage Boot Loader
Release 2019.2  Oct  8 2021-10:22:10

--------------------------------------------------------------------------------
Xilinx First Stage Boot Loader (TE modified)
Release 2019.2  Oct  8 2021-10:22:10
Devcfg driver initialized
Silicon Version 3.1
Watchdog driver initialized
Boot mode is SD
SD: rc= 0
SD Init Done
Flash Base Address: 0xE0100000
Reboot status register: 0x60400000
Multiboot Register: 0x0000C000
Image Start Address: 0x00000000
SD: Unable to seek to 40
          Move Image failed reading FsblLength
Get Header Start Address Failed
Partition Header Load Failed
FSBL Status = 0xA00E

This Boot Mode Doesn't Support Fallback
In FsblHookFallback function
In FsblHookFallback function

[Andrei Errapart]

By chance, do you have series resistors about 40 ohm on the data and clock lines? They should be there to dampen inevitable ringing, which can be easily picked up by the high-speed electronics as false edges. The ESD protectors and EMI filters have them built-in. See https://assets.nexperia.com/documents/application-note/AN10911.pdf for more information. Pullups are required to detect card presence. Most likely you have thought about all that, I just wanted to be sure that this is covered.

I myself have no experience with 1.8V signal levels, maybe others can chime in on that matter.

[jconradt]

Thank you for your suggestion. We have experimented with different series resistors, but no significant change in behavior.

We found a different possible explanation. It seems the Zynq 7000 does not support LVS on the hardware level (technical reference manual ug585, p 368).
There is an older standard implemented on the SDIO interface (2.00), which means that at boot time it would not know how to negotiate LVS.

Can anyone confirm this?
Is there a "work around"?

Thanks for your help! Jörg

[JH]

Hi,
I never test it, but I think it's not possible with SD2.0 Standard from 7 Series Zynq. Xilinx documentation is not clear and I didn't find any Zynq board with 1.8V MIO and direct connected SD card. You need levelshifter or a native 3.3V MIO Bank (on our Module it's 1.8V, because we need 1.8V for some of the other MIO on this bank).
br
John

[jconradt]

Hello!
Thanks for all the help. We now decided to add a level-shifter in our test board, and already with hand-soldered wires and a break-out board for the level shifter, everything works just fine. So for now we will add the TXS02612, or maybe a simpler device).
Thanks again for the replies! Kind regards,

Jörg

[JH]

Hi,
check if the level shifter support SD and if external pullups are still needed or not (this one we use has everything integraded).
br
John