Hi John,
Thanks again for your very quick reply.
From this post:
https://forum.trenz-electronic.de/index.php?topic=737.0It seems that the "Secondary FPGA Image Loaded.." comes from the delivered design.
I get this message even if I try it out in a new TE0722, so it's not something I'm doing myself (I think).
It's also weird, because I search for text saying "Secondary FPGA Image Loaded.." and it doesn't appear in the whole folder where I have the Vitis workspace.
Something that is weird is that although I deactivated the SD card in Vivado, when I compile the application project, it's always generating the
sd_card folder with a boot.bin image...
And if I delete it, when I recompile, it always appears there. Could it be that which it's trying to load?
How could I avoid it being generated during the build?
Thanks,
Jon