Ethernet does not work after adding AXI peripheral

[toka]

Hello,

I already posted my question regarding this topic on the official Xilinx forum with no reply up to now, and want to describe my problem here as well as this community seems to be very active. (You can find my post on Xilinx here: https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/Strange-behavior-of-AXI-EthernetLite-with-other-AXI-periphery/td-p/1258635)

As described there, I am able to run the LwIP echo server on a TE0710 with TE0706-03 perfectly with the startup configuration (see the attached image) of the TE0710 board. The DHCP and auto-negotiation work perfectly as well, though these seem to be problematic in some setups (e.g. non Marvell PHY).

The problem happens, when I add an AXI peripheral like GPIO or Stream FIFO and try to get ethernet connection. The LwIP stops in xemac_add, namely the function XEmacLite_PhyRead waiting for the completion of the transfer (Line 763 of xemaclite.c). I already tried to implement the additional AXI peripherals using interrupts and whithout, the problem is always the same.

Even the removal of the peripheral does not recover the ethernet capability. I can't understand this problem and do not know where to so on with my debugging.

[Antti Lukats]

very weird indeed. We can not advice anything unfortunatly.

[JH]

Hi toka,

you should check timing constrains of the ETH lite IP from Xilinx. When you change something in the design, vivado changed placement and routing of the design, maybe it was luck that it was working before. Check IP user guide for additional constrains which will be not set automatically.

You can also check one times all warnings of your design, maybe there are some which are related to ETH?

Or your project is corrupted now . Sometime the BD file has older content included which will be not longer seen by the editor but by the synthese/implement tools. I see this from time to time,  that's the reason why I use TCL export and complete regeneration of the reference designs. Maybe you should create your Vivado Project one time from scratch.

br
John

[toka]

Hi John,

thank you for the help provided. Unfortunately I was unable to find anything related to timing violations. The timing reports give same results for both designs, with AXI GPIO and without. The IP user guide for the ethernetlite does not mention any timing constraints as far as I saw.

I also checked warnings of the design, there are some ETH-related, but they are same in both implementations, find the messages (all from the synthesis report) here:

Code: [Select]

msys_axi_ethernetlite_0_0_synth_1
[Synth 8-6014] Unused sequential element busFifoData_is_5_d2_reg was removed.  ["c:/Xilinx/test_brd/vivado/TE0710_test_board.srcs/sources_1/bd/msys/ipshared/cae2/hdl/axi_ethernetlite_v3_0_vh_rfs.vhd":5088]

[Synth 8-6014] Unused sequential element busFifoData_is_5_d3_reg was removed.  ["c:/Xilinx/test_brd/vivado/TE0710_test_board.srcs/sources_1/bd/msys/ipshared/cae2/hdl/axi_ethernetlite_v3_0_vh_rfs.vhd":5089]

[Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed.  ["C:/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv":417]

[Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed.  ["C:/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv":417]

[Synth 8-6014] Unused sequential element phy_tx_en_i_p_reg was removed.  ["c:/Xilinx/test_brd/vivado/TE0710_test_board.srcs/sources_1/bd/msys/ipshared/cae2/hdl/axi_ethernetlite_v3_0_vh_rfs.vhd":8302]

[Synth 8-6014] Unused sequential element gen_wr_b.gen_word_wide.addrblsb_reg was removed.  ["C:/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv":1605]

[Synth 8-6014] Unused sequential element gen_rd_b.gen_rd_b_synth_template.gen_rf_wide_reg.addrblsb_reg was removed.  ["C:/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv":2750]

[Synth 8-6014] Unused sequential element reg_access_d1_reg was removed.  ["c:/Xilinx/test_brd/vivado/TE0710_test_board.srcs/sources_1/bd/msys/ipshared/cae2/hdl/axi_ethernetlite_v3_0_vh_rfs.vhd":11572]

[Synth 8-6014] Unused sequential element AXI4_LITE_IF_GEN.write_complete_reg was removed.  ["c:/Xilinx/test_brd/vivado/TE0710_test_board.srcs/sources_1/bd/msys/ipshared/cae2/hdl/axi_ethernetlite_v3_0_vh_rfs.vhd":12951]

[Synth 8-6014] Unused sequential element AXI4_LITE_IF_GEN.read_complete_reg was removed.  ["c:/Xilinx/test_brd/vivado/TE0710_test_board.srcs/sources_1/bd/msys/ipshared/cae2/hdl/axi_ethernetlite_v3_0_vh_rfs.vhd":13107]

[Synth 8-3331] design axi_interface has unconnected port S_AXI_AWID[0]

[Vivado 12-180] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. ["C:/Xilinx/Vivado/2019.2/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl":3]

[Constraints 18-5572] Instance U0/IOFFS_GEN2.DVD_FF has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.

[Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.

[Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.

[Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.


I would be great to have another idea to solve this problem.

[JH]

Hi,
can you test one time our prebuilt binaries (program flash with prebuilt uboot/linux mcs file of your assembly variant ):
https://wiki.trenz-electronic.de/display/PD/TE0710+Test+Board

We use Linux there but you can check one time if the HW is working.

Did you connect ETH cable to the correct ETH connector and did you use the correct on board phy?
TE0710 has to 100Mbit ETH phys and TE0706 has one Gbit ETH phy.
The 2 TE0710 PHY goes to one ETH connector and the TE0706 to the second one.
Only one TE0710 PHY will be detected if you connect cable to the correct connector. You can use the second PHy also when you split for example the cable. Reference Design itself use only one ETH PHY.


In case FPGA Design is the same, then you have a problem with your C code. First check that there is a link up and then see if you can communicate (ping). You could run the Vitis/SDK debugger and see where it gets stuck. I can't help you much with LwIP , I don't have any experience.
br
John

[toka]

I already checked the prebuilt libraries and identified the correct ETH phy, so I am using the right one. As I am able to communicate in the echo server example when no GPIO is installed, I am absolutely sure to use the correct port.

It is very strange, that adding a AXI slave to the design without any interrupt does change the behavior of it, as there should not be any change of the AXI ethernetlite peripheral. Am I right?

Another strange thing is, that even when I remove the AXI gpio, the previous configuration does not work.

[JH]

yes it sounds strange. But it is difficult to help, without seeing all details (this is not part of our free support).

Maybe you have deleted too much and something is not connected or the address space has changed and your SW is looking for the interfaces in the wrong place.

Check if address mapping in your Vivado project is the same like on your exported Vitis BSP and in your own c code.

I would also suggest start with the reference design again, when this works with our linux example. Replace Linux with your new generated baremetal application. if this works, make a backup and start again modification.
br
John

[toka]

Adress mapping is correct, this is one of the first things that I checked.
I will try to follow you advice with the referenc design and Linux.

[toka]

I would like to mention my forum post on Xilinx support forums again, where I just got a very interesting reply: https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/Strange-behavior-of-AXI-EthernetLite-with-other-AXI-periphery/m-p/1262394/highlight/true#M58583

From here, it will be very hard to proceed without help from Xilinx, I guess.

[JH]

Hi,

From here, it will be very hard to proceed without help from Xilinx, I guess.

Maybe maybe not...I can neither confirm nor deny Dan's statement....I'm surprised that it worked for me when I built it and only when you modified it did it cause problems.

What you can try is to open the AXI interconnect IP and enable Register and FIFO on interconnect input and output, maybe this helps, in case the interconnect makes trouble.

I would proceed as follows.
1 Try Prebuilt (you said it would work, so you can skip this point)
2 Build Vivado project with scripts without changing anything and see if it still works (just take the Linux stuff from the prebuilt).
3 replace linux stuff with C software
4 Start modifying of the vivado project if needed.

Make a backup of every working version to narrow down the issue faster when it appears.


br
John

[toka]

Hello,

I might have found the solution. When I use ETH0 instead of ETH1 it works absolutely fine. However, using EHT1 and area optimization for the AXI interconnect I was able to make it work with additional AXI peripheral but it was working by chance when powering up. Could there be a mismatch in the PHY wires for ETH1 so that there is an additional delay which in certain cases works and in others does not?

I will now go on with ETH0.

Thanks for the help so far!

[JH]

Hi,
maybe you should compare BSP import and LwIP defines when you use ETH0 and when you use ETH1, maybe some addressmapping or so is not set correctly when you use ETH1.
But good to hear that you found a workaround for you.
br
John