Author Topic: TE0300 XC3S1200E DDR Control  (Read 8461 times)


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TE0300 XC3S1200E DDR Control
« on: August 29, 2011, 08:01:51 PM »
After all, good afternoon.

We are working with a TE0300 XC3S1200E Board, but in the implementation we have a problem, the DDR never initialize.

We generate a MIG and Develop a module to control the MIG, we test the code with a TEST_BENCH and in a Digilent Spartan-3E Starter Kit Board that have the same DDR Device than the TE0300 XC3S1200E FPGA Board, and it works correctly.

We observed that in the Trenz Electronic Board, the signal named cntrl0_sys_rst180_tb that becomes from the MIG module, never go to falling edge.

It is supossed that the cntrl0_sys_rst180_tb signal becomes to a falling edge when the DDR stabilize their voltage.
What are the possible error that cause that issue?

Can anyone have a MIG module with the UCF file for that Device?

Ales Gorkic

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Re: TE0300 XC3S1200E DDR Control
« Reply #1 on: September 01, 2011, 11:31:50 PM »
Dear progman64,

Sorry for a bit late response, but I have found an original UCF file from the MIG 2.3.
I have also compared the pinout from our design and the MIG generated one. The only differences are locations of the pins.
Our pins with modified locations:
NET  "cntrl0_ddr_cke"                                LOC = "T17" ;   
NET  "cntrl0_ddr_we_n"                               LOC = "U16" ;
NET  "reset_in_n"                                    LOC = "T16" ;

But be very careful with the reset: the MIG reset is active LOW, while our pusbutton is active HIGH! That is why your controller is always in reset state i presume.
I have left the "reset_in_n" in original position, just adding a PULLUP directive to prevent pin floating.

We also use 100 or 125MHz oscillator at location (not specified in the MIG ucf):
Net sys_clk_pin LOC=U10;

I have put the original MIG project on the Trenz Electronic reference designs repository with corrected UCF files:

Best regards,

« Last Edit: April 17, 2012, 06:28:48 PM by Hengist »