Author Topic: PL CLK_0 cannot change the frequency  (Read 1178 times)

jarios86

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PL CLK_0 cannot change the frequency
« on: May 27, 2021, 10:50:56 AM »
Hi all,

I have problems with the pl_clk_0 clock frequency. It seems not to change when I modify its frequency in the zynqu+ IP core in Vivado. Let's start explaining my setup:
- Baseboard TEBF0808-04A
- Module TE0808-04 XCZU15EG-1FFVC900E

I have used the block design that trenz provides for vivado 2018.2 in the Starterkit. I have added some GPIOs IP core and a custom IP core in my hardware design and set the pl_clk_0 to 50MHz in the zynqu+ IP core. I synth and impl my design with no error. After that, I have exported the hardware, including the .bit file, to create a petalinux project. I have used the petalinux project provided in the same Starterkit and configured using the exported hardware. Everything works fine but the PL clock frequency (pl_clk_0) is 100MHz instead of 50MHz. To measure the real clock frequency I have routed the pl_clk_0 to an output pin and checked it using the scope. Attached you can find the scope screenshot.

To create the boot.bin I use zynqmp_fsbl.elf, u-boot.elf, bl31.elf, and zynqmp_pmufw.elf provided in the Starterkit too.

I have changed the pl_clk_0 clock frequency to different values but the behaviour of my system is always the same and the clock frequency measured in the scope is always 100MHz.

Please, I would appreciate any help.

Best regards,
Antonio

JH

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Re: PL CLK_0 cannot change the frequency
« Reply #1 on: June 01, 2021, 03:19:10 PM »
Hi,
you must regenerate all sources in case you change something on PS.

PS-PL CLKs will be initialised by FSBL which depends on your XSA from your vivado project. In case you use Linux, also linux must be regenerated(minimum device tree), because linux can control also PS-PL clks.



br
John

jarios86

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Re: PL CLK_0 cannot change the frequency
« Reply #2 on: June 02, 2021, 03:58:04 PM »
Hi John,

Thanks a lot for your response.

In my case, I configure the petalinux project using the exported hdf file from vivado and then compile petalinux. To create the BOOT.BIN file I use the zynqmp_fsbl.elf in the Starterkit provided by Trenz, because if I use the one resulting from petalinux compilation, the system boots but the USB ports are not available.

So, to change the PS-PL clocks I should import the hdf file in the FSBL project provided in the Starterkit, and then use the resulting zynqmp_fsbl.elf file to create the BOOT.BIN petalinux file. Am I right?

Thank you for your comments.

Best,
Antonio

JH

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Re: PL CLK_0 cannot change the frequency
« Reply #3 on: June 07, 2021, 07:01:54 AM »
Hi,

Quote
because if I use the one resulting from petalinux compilation, the system boots but the USB ports are not available.
you must write a fsbl patch to add our FSBL changes also on petalinux generated FSBL. Or use simple Vitis to generate FSBL and boot.bin .

Quote
So, to change the PS-PL clocks I should import the hdf file in the FSBL project provided in the Starterkit, and then use the resulting zynqmp_fsbl.elf file to create the BOOT.BIN petalinux file. Am I right?
yes

br
John