clk ports of TE0726

[Gloria]

Hi, I have a project with a port sys_clk，and I need to create constrains for sys_clk. However, I do not know the clock ports that can be used in TE0726. I do not find in reference and the schemetic.
Could you please help me check the clock ports in TE0726?

[JH]

Hi,
 what did you mean?

You need a CLK for a PL IP? Use simple one of the 4 PS-PL CLKs which are available from the PS --> CLK freq can be set with PS IP (When you change something in the PS IP, regenerate FSBL and Linux to otherwise you design use old setting)

br
John

[Gloria]

yes, but I do not use zynq ip in my project. So I think I can not use the clk generated by zynq ip.
I want to constrain the sys_clk in my project and I do not know which pin can be use, I try the ports in the picture, but vivado says that there is no valid ports

[JH]

Hi,
you need PS on this module to get a on board CLK on PL available.
In case you didn't used PS, still instantiate PS with our board files (or use the test board reference design). Configure PS-PL CLKs like you want, export xsa and generate FSBL and boot.bin with this FSBL --> Configure Flash with this Boot.bin and reboot the board. Now PS is initialised and you can reprogram PL only with bitstream and you has a valid CLK.

br
John

[Gloria]

Hi，I get it. Thank you!