Author Topic: TE0713-020 Si5338 Configuration  (Read 96 times)

jt

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TE0713-020 Si5338 Configuration
« on: April 26, 2021, 09:06:47 PM »
How does the TE0713-020 get configured in the reference design? I do not see an I2C connection to program the Si5338, but presumably this Si5338 gets programmed as the reference design works.

I tried to create a blank project and use the 200MHz input clock, but it does not appear to work after boot in a blank project.

Thanks in advance for your help.

JH

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Re: TE0713-020 Si5338 Configuration
« Reply #1 on: April 27, 2021, 06:56:24 AM »
Hi,
SI5338 is preprogrammed,
https://wiki.trenz-electronic.de/display/PD/TE0713+TRM#TE0713TRM-Clocking

 We have some reference design online, which use this CLK:
https://wiki.trenz-electronic.de/display/PD/TE0713+Test+Board


For SI5338 reconfiguration on runtime, you should check the project of TE0712 (it's similar board ):
https://wiki.trenz-electronic.de/display/PD/TE0712+Test+Board
We use MCS (small microplace) with independent config CLK there to reconfigure SI5338

br
John




jt

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Re: TE0713-020 Si5338 Configuration
« Reply #2 on: April 30, 2021, 02:57:56 AM »
The 200MHz input clock does not come up for me by default.

I have created a project with a simple counter below and added an ILA to view the counter. You may need to edit the path to the vivado executable in ~/scripts/run.tcl to build the project.

JH

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Re: TE0713-020 Si5338 Configuration
« Reply #3 on: April 30, 2021, 07:31:36 AM »
Hi,
which IOs did you use for the 200MHz CLK? Which IO standard did you set?

Can you try out the prebuilt binaries of our reference design. This will use the 200MHz CLK.

https://wiki.trenz-electronic.de/display/PD/TE0713+Test+Board

Write simple bitstream and check DDR inti cal status on Vivado HW Manager:
https://wiki.trenz-electronic.de/display/PD/TE0713+Test+Board#TE0713TestBoard-VivadoHWManager

for full test you must write mcs into flash.
br
John

jt

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Re: TE0713-020 Si5338 Configuration
« Reply #4 on: April 30, 2021, 04:40:52 PM »
I am using H4/G4, DIFF_SSTL135_R:

Code: [Select]
set_property PACKAGE_PIN H4 [get_ports CLK_200_P]
set_property PACKAGE_PIN G4 [get_ports CLK_200_N]
set_property IOSTANDARD DIFF_SSTL135_R [get_ports CLK_200_*]

I am able to run the reference design, which is why I don't understand why I can't just immediately use the 200MHz clock. I do receive some invalid characters over the UART while the SREC loads:


SREC SPI Bootloader (TE modified): Start initialization

SREC SPI Bootloader (ÔC*ªQ(H*TRH¡ë
                                  ë+V.$JUQH[
                                            VËV«V%'H*®X.]HZ·Z]ZX¶Z½XºZ?H¨HhUÔ(¤*TR¡ootloader (TE modified): SPI driver Init passed

SREC SPI Bootloader (TE modified): Serial Flash Library Init passed

SREC SPI Bootloader (TE modified): Load Image
Loading SREC image from flash @ address: 005e0000
Please wait...ERROR: Error while reading an SREC line from flash--Starting Memory Test Application--
NOTE: This application runs with D-Cache disabled.As a result, cacheline requests will not be generated
Testing memory region: mig_7series_0_memaddr
    Memory Controller: mig_7series_0
         Base Address: 0x80000000
                 Size: 0x40000000 bytes
          32-bit test: PASSED!
          16-bit test: PASSED!
           8-bit test: PASSED!
--Memory Test Application Complete--


When I add I/O to the reference design block diagram, they get treated as ports at the top level which causes I/O placement errors. How do I create new I/O within the reference block diagram without creating these errors.

Also, which FPGA I/O controls the LED on the board?

Thank you for your help.

JH

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Re: TE0713-020 Si5338 Configuration
« Reply #5 on: May 04, 2021, 06:53:37 AM »
Hi,
Quote
set_property PACKAGE_PIN H4 [get_ports CLK_200_P]
set_property PACKAGE_PIN G4 [get_ports CLK_200_N]
set_property IOSTANDARD DIFF_SSTL135_R [get_ports CLK_200_*]
this should be OK, it's the same like on the reference design.

I would suggest to add clockbuffer to this CLK and connect them directly to XIilinx Debug VIO core and also to a MMCM (configure without input buffer), so you can use VIO core to check MMCM status.

Quote
I do receive some invalid characters over the UART while the SREC loads:
I think this is not critical, it's some misinterpretation. Did you use longer cable or so?

Quote
When I add I/O to the reference design block diagram, they get treated as ports at the top level which causes I/O placement errors. How do I create new I/O within the reference block diagram without creating these errors.
Use Xilinx IO planner after synthesis to setup missing IO constrains



Quote
Also, which FPGA I/O controls the LED on the board?


https://wiki.trenz-electronic.de/display/PD/TE0713+CPLD#TE0713CPLD-LED
FPGA_IO1 is  FPGA Pin K4, see schematics page 7
https://shop.trenz-electronic.de/de/TE0713-02-200-2C-FPGA-Modul-mit-Xilinx-Artix-7-XC7A200T-2FBG484C-4-x-5-cm-1-GByte-DDR3L?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0713/REV02/Documents

br
John