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Spirit Level example design without NIOS


Hi to all, I tried the accelerometer on the CYC1000 FPGA board. The result is the Spirit Level example (without NIOS) for CYC1000 in my GitHub repository with SPI controllers. In this repository I also started using GHDL tool in GitHub Actions to automate my VHDL simulations. It is an easy-to-use CI for VHDL projects. You can use it as inspiration.

Thanks a lot, that's all I was looking for!


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