Author Topic: HLS IP doesn't write correctly to PS RAM  (Read 79 times)

johnabel

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HLS IP doesn't write correctly to PS RAM
« on: April 22, 2021, 09:40:19 AM »
I wrote an IP with HLS that writes the PS RAM using a master AXI port and I found it only writes the first 4 bytes of each 16-byte group.
After a couple of weeks, I tried on a different board, an MYD-CZU3EG (instead of TE0803) and, boom, works like a charm.
Looking at the differences between these boards, the DDR RAM chips are different as well as the timing settings in the PS configuration.
I wonder if these settings could be wrong (maybe a batch of boards with a different DDR chips?) or not appropriate for PL-PS access?
Or could there be another reason causing that?

Oleksandr Kiyenko

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Re: HLS IP doesn't write correctly to PS RAM
« Reply #1 on: April 22, 2021, 09:52:45 AM »
Hello.

You can check DDR settings by standard memory test, but I think that the problem is not in the
memory configuration. With a wrong memory configuration, the board will not start or freeze after a few seconds.
You need to check the difference in the PL-PS interface. Try to add ILA to this interface and compare the AXI transactions.

Best regards
Oleksandr Kiyenko

johnabel

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Re: HLS IP doesn't write correctly to PS RAM
« Reply #2 on: April 23, 2021, 02:15:55 PM »
Yes, I would expect that: wrong settings = nothing works. But wasn't sure if there could be a border condition affecting certain types of access.
Anyways I sorted it out by setting the width of the AXI port the PL uses to access the PS memory. 128 bit width makes it work. 32 doesn't. I didn't test 64.
I don't know the reason, especially if a similar board works with width 32 and another doesn't.