Author Topic: Unable to drive GPIO output from bare metal application on Cortex R5 in TE0802  (Read 128 times)

jsm

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Hi all,

I am trying to drive a GPIO pin directily from a bare metal program running on the R5F of an TE0802, without routing it through the FPGA, but directly using MIO18 instead, which goes to the Grove connector. The A53 is only running the boot loader.

I have reconfigured the Trenz HW specification in Vivado to disable I2C and enable GPIO on MIO18 and MIO19. However, the following code does not work, the pin is always high, any ideas?


#define GPIO_PIN                   18
#define GPIO_OUTPUT_DIR   1
#define GPIO_LOW                 0
#define GPIO_HIGH                1

XGpioPs gpio;
XGpioPs_Config *gpio_cfg = XGpioPs_LookupConfig(GPIO_DEVICE_ID);
int gpio_status = XGpioPs_CfgInitialize(&gpio, gpio_cfg, gpio_cfg->BaseAddr);
if (gpio_status != XST_SUCCESS) {
    printf("ERROR: could not initialize gpio driver \r\n");
}

XGpioPs_SetDirectionPin(&gpio, GPIO_PIN, GPIO_OUTPUT_DIR);
XGpioPs_SetOutputEnablePin(&gpio, GPIO_PIN, 1);

while(1) {
    usleep(50000);
    XGpioPs_WritePin(&gpio, GPIO_PIN, GPIO_LOW);
    usleep(50000);
    XGpioPs_WritePin(&gpio, GPIO_PIN, GPIO_HIGH);
}





JH

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Hi,
did you enable also these Pins as GPIO in your Vivado IP and export the new XSA (on older vivado HDF) Files for your Vitis Project (SDK on older Vivado versions)?

Work your code with A53?
Xilinx has some additional information here:
baremetal:
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841745/Baremetal+Drivers+and+Libraries
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841744/Gpio-PS+standalone+driver
linux:
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842398/Linux+GPIO+Driver

br
John

jsm

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Thanks John.

That's right, I enabled these pins in Vivado (property of ZynqMP IP in block design), then Synthesis, Implement, Bitstream and export hardware xsa.

After that, I reloaded the new xsa in Vitis, rebuilt project and used the code I described earlier. I have not tried A53, in fact I am just starting with this board and I am only using the R5 side. I can printf from the Cortex R5 (JTAG console) but I am unable to drive a GPIO pin. I have also tried to reconfigure the pins linked to the SD card, but no luck.

I know that the PL can be used to connect the R5 to the Pmod connector, using EMIO, but I don't want yet to follow that route as I don't have experience with FPGAs, nor the time to learn about that right now.

JH

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Hi,
Quote
That's right, I enabled these pins in Vivado (property of ZynqMP IP in block design), then Synthesis, Implement, Bitstream and export hardware xsa.
do not "reload" try to create completely new Vitis project with this XSA file. Vitis is new, I've seen that XSA reload sometimes not work like expected. I don't know if this is the reason but you should try out this one time

Quote
After that, I reloaded the new xsa in Vitis, rebuilt project and used the code I described earlier. I have not tried A53, in fact I am just starting with this board and I am only using the R5 side. I can printf from the Cortex R5 (JTAG console) but I am unable to drive a GPIO pin. I have also tried to reconfigure the pins linked to the SD card, but no luck.
what did you means configured like SD card? On Vivado IP there will be special selections boxes for GPIO MIO, in case they are not used on other interfaces.

EMIO or MIO both should work, EMIO uses only other drivers later but in both cases it should be enabled correctly. EMIO need later only programmed PL part with correct bitstream, which is normally done when you put the correct bitstream into your boot.bin to your FSBL and application.
br
John

jsm

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Hi,do not "reload" try to create completely new Vitis project with this XSA file. Vitis is new, I've seen that XSA reload sometimes not work like expected. I don't know if this is the reason but you should try out this one time
You are right, I created a new project using the previous XSA and now it works!

Quote
what did you means configured like SD card? On Vivado IP there will be special selections boxes for GPIO MIO, in case they are not used on other interfaces.
I meant that in Vivado, I just disabled the SD peripheral in the PS so that the SD pins are configured as GPIO. I just wanted to try something else in addition to the Grove connector, but now I get output through the Grove connector so this is not necessary

Quote
EMIO or MIO both should work, EMIO uses only other drivers later but in both cases it should be enabled correctly. EMIO need later only programmed PL part with correct bitstream, which is normally done when you put the correct bitstream into your boot.bin to your FSBL and application.

The problem with EMIO is that, as far as I know, the default Trenz project does not include PL blocks that connect EMIO in the PS to the PMod connector. And I don't know how to program the FPGA, still a lot to learn.

Thanks a lot for your help, John!
Juan.

JH

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Quote
The problem with EMIO is that, as far as I know, the default Trenz project does not include PL blocks that connect EMIO in the PS to the PMod connector. And I don't know how to program the FPGA, still a lot to learn.

  • Enable EMIO on PS IP.
  • Forward IP EMIO Pin as external Pin
  • synthesise IP and open Pin planner
  • assign Pin
  • create Bitstream, export xsa to Vitis
  • create software and Boot.bin which includes all need files
Try out a little bit, In the end, this is not much harder than MIO GPIO.

br
John