Author Topic: TE0715 constraint and board files question  (Read 141 times)


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TE0715 constraint and board files question
« on: March 11, 2021, 11:23:12 PM »
Hi there,

I'm looking at using a Trenz module for an upcoming commercial project however I'm unsure due to the lack of documentation and constraints.

Specifically, we are looking at using the TE0715-04-12S-1C module and I can't seem to find any constraints files or documentation surrounding the DDR memory timing used on the board. It seems crazy that modules could be sold without this support, what would be the point in the module?

The technical reference manual is pathetic, under the DDR memory section it simply says DDR memory exists!

Any help would be appreciated!


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Re: TE0715 constraint and board files question
« Reply #1 on: March 12, 2021, 06:03:48 AM »
we have a reference design online for different assembly options of the TE0715:
Download includes prebuilt binaries (baremetal hello world and linux) to test and also source code and board files with PS setup (include DDR).
Current project is for Vivado/Vitis/Petalinux 19.2 .

Update to 20.2 is planned (we must solve some problems with 20.2 at first (Xilinx has changed a lot of things especially for linux part))

Links to other documentation and downloads:

For PL loc constrains see our excel sheet for 4x5 module:
--> 4x5_series_pinout_tracelength.xlsx