Attention: For security reasons,please choose a user name *different* from your login name.
Also make sure to choose a secure password and change it regularly.

Main Menu

TE0741 Module signal vs pin/package vs routed length xls file

Started by, January 29, 2021, 10:04:39 AM

Previous topic - Next topic


I am using a TE0741-03-325-2CF module, in particular I have to route some LVDS lines.

Firs of all, in Vivado I have a .csv file that specify each pin delay,
e.g.  IO_L1P_T0_12 has a delay that is more or less 96 ps (95.7; 96.7 ps) instead IO_L1N_T0_12P is 102 ps (101.7 and 102.7 ps) that mean a skew (P-N) of -6 ps with an dispersion of +/- 1 ps due to the dispersion of the P and N delays.

On your xls file I see that the IO_L1P_T0_12 and IO_L1N_T0_12P become the B13_L1_P and B13_L1_N.
I see 3 different length: signal, pin/package and routed in mm. What is the meaning of this 3 name?

I presume that:
- routed length is the length in your TE0741 PCB design
- pin/package is the conversion in mm of the delay in ps present in xilinx's cvs file
- signal is the sum of routed and pin/package

Is it correct? in fact for some signals routed + pin/package is different to the signal length.
Have you compensated the _P/_N skew of the FPGA package inside each PCB or I have to do this on my carrier board? Which length I have to inserti in Altium for the _P/_N skew matching?



our excel sheet includes only PCB length. Package length is not included.
We have also a second excel table now which show cross reference to our carrier:

IO_L1P_T0_12 and IO_L1N_T0_12P are Xilinx device Pin names, description:
page 28 ff
--> But you mean IO_L1P_T0_13 IO_L1N_T0_13 ? See Schematics page 4. I think you has the wrong bank selected on your screenshot

B13_L1_P and B13_L1_N are schematic names:
B13 (mean bank13) and L1 are related to Xilinx documentation and N/P also for polarity and that this pins belongs together in case of differential usage.


Hi John, thanks for your support, but we need some more help.
Yes, our screenshot and our question was wrong, in fact we have messed up with banks numbers.... I'll try to make my question more clear.

We found this file on the TM0741 download page:
In this file there are 3 columns indicating 3 different length. We are trying to understand what these numbers are indicating.
We found out that the "Pin/Package Length" column contain a number that is exactly the pin delay due to package (as indicated by xilix) multiplied by 0,149mm/ps.
So we are wondering if you have considered this package mismatch during the matching of the p/n pairs on the TE module.

At the end of the day we are trying to have a carrier board that is compatible with several TE modules. So IF your module is matched considering the internal package mismatch between P/N pins, we can achieve the desired compatibility.
Consider that in our specific application, we are using a bounch of differential lines, but we are NOT interested in the length matching between pairs but only in the matching of the P/N tracks within each signle line.


package length can differ on different footprint compatible packages and FPGA size which can be assembled on the same PCB. We take this into account but we can't archive full length match for all possible assembly variants.
You wrote
Quotet the end of the day we are trying to have a carrier board that is compatible with several TE modules.
Inside one series or on different series?
You must not archive 100% length matching normally. Tolerance depends on IO standard and speed which you used.