TE0712 Ref Design problems: "Cannon stop MicroBlaze, Processor held in reset"

[tschesnok]

I just managed to fire up my TE0712 Module (Artix-7 - 100 2c) on the 701Rev6 base board.

I managed to create the corresponding reference design for Vivado, got it built and exported the bitstream.. launched Vitis.
In Vitis I created an app running "standalone", built it and managed to program the FPGA module via the USB/CPLD on the 0701.

I then get Cannot stop MicroBlaze, Processor held in reset.

Any thoughts? This is the te0712 reference design with zero changes. (correct version for 100-2c). Running 2019.2 tools and reference. I noticed that a reset pin is linked to the Artix-7 pin "T3" which is not connected to anything. Constraint file pulls it low.. and the reset is setup as active high. So while it does nothing it also does not seem to be the problem.

Any ideas? Is this a Vitis issue?

Many Many thanks.

[tschesnok]

I did get the Microblaze working by building a DDR3 Vivado HW config  from scratch. Perhaps this is a Vitis / Linker Script configuration issue?

[JH]

Hi,
Reference design used a second microblaze (MCU) which will be used to reprogram SI5338.  It will hold main Microblaze into reset, in case you has use it without firmware running on it.

You can check reset state with Vivado HW Manager and VIO core: https://wiki.trenz-electronic.de/display/PD/TE0712+Test+Board#TE0712TestBoard-VivadoHWManager:

MCU firmware:

    https://wiki.trenz-electronic.de/display/PD/TE0712+Test+Board#TE0712TestBoard-scu.1
    Template location: ./sw_lib/sw_apps/

br
John

[tschesnok]

Thank you. I did get it working.