GigaBee Questions

[bmadsen]

Hello

We have recently bought a couple of GigaBee boards, and I have some questions.

First off, the user manual found in the download area has page numbers indication that it should be 79 pages, but it is only 14 pages long. It jumps from page 28 to 67. Is this an error, or is this all there is?

When loading the "GigaBee_XC6SLX_webserver-ISE_13_1" project, XPS tells me that there is an invalid path specified for ModuleSearchPath. The offending line in the .xmp file is:

Code Select Expand

ModuleSearchPath: ../../../../IpCores-ISE/

After this there are some warnings about superseded IP cores and the project stops loading when an IP core for "plb_onewire" cannot be found. Is this an oversight on your part, or have I done something wrong in the setup of ISE?

Thanks in advance

-Bjørn

[Thorsten Trenz]

Dear Bjørn,

First off, the user manual found in the download area has page numbers indication that it should be 79 pages, but it is only 14 pages long. It jumps from page 28 to 67. Is this an error, or is this all there is?

The manual is still work in progress. We will finish it as soon as possible. If there are any doubts, please do not hesitate to ask.

When loading the "GigaBee_XC6SLX_webserver-ISE_13_1" project, XPS tells me that there is an invalid path specified for ModuleSearchPath. The offending line in the .xmp file is:

Code Select Expand

ModuleSearchPath: ../../../../IpCores-ISE/

After this there are some warnings about superseded IP cores and the project stops loading when an IP core for "plb_onewire" cannot be found. Is this an oversight on your part, or have I done something wrong in the setup of ISE?

You need to checkout the also the following:
https://github.com/Trenz-Electronic/TE-EDK-IP/
https://github.com/Trenz-Electronic/TE060X-GigaBee-Reference-Designs/

best regards
Thorsten Trenz

[bmadsen]

Thanks

[Ales Gorkic]

Dear Bjorn,

I suggest you first test the new AXI designs if you are using Xilinx Suite v13.x. This ones were designed with 13.1 and offer maximal performance.
The GigaBee_XC6SLX_webserver-ISE_13_1 was not yet fully ported to 13.x (software problems).

Best regards,

Ales

[bmadsen]

Ok, will do that. Thanks again for the swift responses

[bmadsen]

So, I tried building the GigaBee_XC6LX-Axi project. After almost an hour it failed with the following messagE:

Code Select Expand

xflow done!
touch __xps/system_routed
xilperl /opt/Xilinx/13.1/ISE_DS/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par
********************************************************************************
ERROR: 1 constraint not met.

PAR could not meet all timing constraints. A bitstream will not be generated.

To disable the PAR timing check:

1> Disable the "Treat timing closure failure as error" option from the Project Options dialog in XPS.

OR

2> Type following at the XPS prompt:
XPS% xset enable_par_timing_error 0
********************************************************************************
Analyzing implementation/system.par
make: *** [implementation/system.bit] Error 1
Done!

Will it still work if I disable the "Treat timing closure failure as error" option from the Project Options dialog in XPS?

[Ales Gorkic]

Hi OR,

I had the same problems at the beggining. The microblaze did not meet timing.
If the timing is not met then there is no guarantee that it will work. With low timing result it usually works.

I have corrected this by removing the branch target cache.

Can you check the system.mhs line 109 and set to:
PARAMETER C_USE_BRANCH_TARGET_CACHE = 0

The AXI-lite did not exhibit this problems due to lower complexity.

Best regards,

Ales

[bmadsen]

Hello again

The constraint that wasn't met was:

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TS_host_clk = PERIOD TIMEGRP "host" 10 ns HIGH 50% PRIORITY 10

Line 109 in system.mhs already is

Code Select Expand

PARAMETER C_USE_BRANCH_TARGET_CACHE = 0

[bmadsen]

I've run into a new problem. We are running the board with the XC6SLX45, and so far both the AXI and the AXI lite project fail to build, due to a placement error for MCB_DDR3/MCB_DDR3/mcb_ui_top_0/gen_spartan6_bufpll_mcb.bufpll_0

[bmadsen]

And now I found the commented lines in the ucf files. It builds now!

[Ales Gorkic]

Hi Bmadsen,

I have tried the AXI-lite project on the GigaBee LX45. It does not work out from the box. The design boots normally, but I get no response from the ethernet.
Did you manage to run it with success?

Best regards,

Ales

[bmadsen]

No, I tried some changes, but to no avail. In the end we managed to get the regular AXI project running, but due to other projects, I haven't done much more than that.

[Ales Gorkic]

To me it seems that connection is not detected at AXI_lite project. Still searching for clues.

The AXI project had MDIO address set wrong (now PARAMETER C_PHYADDR = 0B00111). I have corrected it in system.mhs
Have you found any other things?

Best regards,

Ales

[bmadsen]

Actually the AXI project worked fine for me directly. Although I've only tried the echo server. For now I'll be away for a week, after that I'll report back on any new issues I might find.

[Vknen]

I would be happy if someone could help me to get AXI reference design to work. I am using gigabee with LX150 version of spartan 6. I run the platform studio and generated bitsream succesfully with recommended changes on ucf file (changed device and delays). I have exported my design to SDK and imported socket_apps and socket_bsp projects. When trying to build bsp project the following errors are displayed:

Running libs - 'make -s libs "COMPILER=mb-gcc" "ARCHIVER=mb-ar"
"COMPILER_FLAGS=-mlittle-endian -mno-xl-soft-mul -mxl-multiply-high
-mxl-barrel-shift -mxl-pattern-compare -mhard-float -mxl-float-convert
-mxl-float-sqrt -mno-xl-soft-div -mcpu=v8.10.a  -O2 -c"
"EXTRA_COMPILER_FLAGS=-g"'.
Compiling standalone
Compiling common
Compiling llfifo
/usr/bin/sh: -c: line 3: syntax error: unexpected end of file
make[2]: *** [arch-libs] Error 258
make[2]: Target `libs' not remade because of errors.
.
.
.
.
ERROR:EDK:369 -  make failed for target "libs"
ERROR:EDK:3418 - Error(s) while running make.
make: *** [microblaze_0/lib/libxil.a] Error 2
make: Target `all' not remade because of errors.

[Thorsten Trenz]

Hi,
did you use the GigaBee_XC6LX-Axi from https://github.com/Trenz-Electronic/TE060X-GigaBee-Reference-Designs ?
Did you use also ISE13.2 as written in the readme?

best regards
Thorsten Trenz

[Vknen]

I downloaded version 13.2 of EDK and unzipped GigaBee_XC6LX-Axi from github to new folder. I opened EDK and imported only hw_platform_0 and socket_bsp projects. I tried to build socket_bsp and same errors occurred.

I found similar error report from xilinx forums: http://forums.xilinx.com/t5/EDK-and-Platform-Studio/Errors-making-bsp-when-following-UG670-EDK-13-1/td-p/139950

People are suggesting that problem lies on make tool version. I will try next to use newest version of EDK if it helps.

[Oleksandr Kiyenko]

Hello Vknen
I just download GigaBee_XC6LX-Axi-EDK-13.2-v1.0.580857a from Github and build it without errors on EDK 13.2.
I did:
1) Build hardware
2) At EDK interface press "SDK" button and "Export & Launch SDK"
3) create new workspace
4) Import socket_bsp to this workspace and midify properties to use new hardware platform
5) Import socket_apps

Please give me more detailed description of your problem. How you building your project step by step.

Regards
Alex