Author Topic: TE0720 ATSHA204 access  (Read 271 times)


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TE0720 ATSHA204 access
« on: November 21, 2020, 10:15:00 AM »
If I interpret the CPLD description and the ATSHA204 documentation correctly, the best way to access the ATSHA204 is to route Zynq pin M15 (aka X2 aka XIO4) to EMIOUARTnRX and EMIOUARTnTX to Zynq pin N15 (aka X3 aka XIO5).
Since by default the CPLD will drive PHY_LED1 to XIO5, I have to set CPLD CR2 bits 7:4 to 0110. To get the output of the ATSHA204 on XIO4 I have to set CR2 bits 3:0 to 0010.

I don't see any resistor between Zynq pin N15 and the corresponding CPLD pin. Is it safe to push-pull drive N15 before CR2 is configured?
Or does the CPLD drive XIO5 open drain so that I can safely do the same with N15?
Or do I need logic to tri-state N15 until CR2 bits 7:4 are set to 0110?

Antti Lukats

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Re: TE0720 ATSHA204 access
« Reply #1 on: November 23, 2020, 08:39:17 AM »

the CPLD drives push-pull but you can drive from the FPGA also, even if there is conflict it does no harm, the io currents are all limited.

Antti Lukats