Two Ethernet with TE0821 + TE0706 on 2019.2

[VP]

Hi,

We mange to get the two ethernet ports of the TE0706 with the TE0720 module and 2018.3 following your reference design.

Is there any reference design to do the same with the TE0821 or TE0820 modules?

Our Vivado design is the same as with the TE0720.


So far, during u-boot, it stays for very long (about 1 minute) on this line:

Code: [Select]

Net:   ZYNQ GEM: ff0c0000, phyaddr 0, interface gmii
After that, petalinux boots but only one ethernet interface is available:

Code: [Select]

[    3.835590] macb ff0c0000.ethernet: Not enabling partial store and forward
[    3.842937] libphy: MACB_mii_bus: probed
[    3.846970] xgmiitorgmii ff0c0000.ethernet-ffffffff:08: Couldn't find phydev
[    3.854179] zynqmp_pll_disable() clock disable failed for dpll_int, ret = -13
[    3.885991] macb ff0e0000.ethernet: Not enabling partial store and forward
[    3.893315] libphy: MACB_mii_bus: probed
[    3.897239] [Firmware Warn]: /amba/ethernet@ff0e0000/ethernet-phy@0: Whitelisted compatible string. Please remove
[    3.981614] Marvell 88E1510 ff0e0000.ethernet-ffffffff:01: attached PHY driver [Marvell 88E1510] (mii_bus:phy_addr=ff0e0000.ethernet-ffffffff:01, irq=POLL)
[    3.995522] macb ff0e0000.ethernet eth0: Cadence GEM rev 0x50070106 at 0xff0e0000 irq 30 (80:1f:12:c2:2a:5d)

This is the device tree for the &gem1 and &gem3.

Code: [Select]

&gem1 {
local-mac-address = [00 0a 35 00 01 23];
  phy-handle = <&phy1>;
status = "okay";
xlnx,has-mdio = <0x1>;
psu_ethernet_1_mdio: mdio {
#address-cells = <1>;
                #size-cells = <0>;

  phy1: ethernet-phy@0 {
        device_type = "ethernet-phy";
            reg = <0>;
};
gmii_to_rgmii_0: gmii_to_rgmii_0@8 {
                        phy-handle = <&phy1>;
                        reg = <8>;
                };
    };
};


&gem3 {
 
    status = "okay";
  ethernet_phy0: ethernet-phy@0 {
        compatible = "marvell,88e1510";
        device_type = "ethernet-phy";
            reg = <1>;
    };
};
Thanks in advance,

Vicente.

[JH]

Hi,
sorry we haven't any special reference design at the moment for this combination of carrier and module.
it looks like phy address is wrong because he didn't get answer from the phy.
br
John

[VP]

Hi,

We manage to get both ethernet interfaces up and running in Linux. The problem was that we were using the prebuilt FSBL provided from the reference design. The RGMII2RGMII and other Vivado changes were not properly initialised with that FSBL. Once we compile our own FSBL with TE modification (SI5338 and ETH and USB resets) it work as expected.

However, we noticed that the performance of the two interfaces is quite different.

eth0 uses the PHY on the TE0706 with the GMII2RGMII IP in between, and we can get a maximum of 126 Mbits/s (iperf).
eth1 uses the PHY on the TE0821 and we can get about 950 Mbits/s as expected (iperf).

Both interfaces auto-negotiate properly to 1000 Mbits/s.

Just for comparison purposes, using the TE0706 + TE0720 and your reference design with two ETH, we get identical performance on both interfaces.

Looking at eth0 signals, we found that ETH-RXCK and PHY_INT on the TE0821 goes connected to CLKIN_P and CLKIN_N respectively. This is one of the inputs of the onboard (TE0821) TI5338.

• For ETH-RXCK, we are using the JB3-58 pin on the TE0706. Is there a way to route PHY_INT to the FPGA?
  
• Does it means we cannot use the TE0706 with the TE0820 or TE0821?
  

We developing our own carrier board based on the TE0706, but we want to make sure everything works on the TE0706.

Thank you again,

Vicente.

[JH]

Hi,

The problem was that we were using the prebuilt FSBL provided from the reference design.

Prebuilt FSBL is only for the configuration which was used in the Reference design.  When you change something on PS or PS-PL interface or when you change Vivado/Vitis/Petalinux version. you should always regenerate FSBL.
FSBL, uboot and linux setup many things separately but they work together. So as long as you didn't regenerate all files when you make changes, you can still have problems.

RX Pin depends on IP restriction. TE0706 was created for 7 Series and we add 2 possible Pins for RXCK (depending on the package which was used), see TE0706 schematics page 3, JB3 and JB58. there are zero ohm resistors to disconnect one of the pins if necessary.


I don't know the restriction from the GMII to RGMII IP from Xilinx for U+ Zynq which is used on TE0820/TE0821. But when you get it running, I think you sue this one of JB58?
PHY_INT is optional and depends on your PHY configuration (which will be done by drivers or your device tree), but this can't be used on TE0820/TE0821 modules.

I didn't make any performance test, but I think this is a problem of the drivers. Xilinx has often problems to use more than one ETH out of the box without modifications and patches.


br
John

[VP]

Hi,

We found the problem and solved our issue!

By removing R18 from the TE0706 the performance is as expected (900+ Mbit/s up-down on both interfaces). With R18 ON and hence RXCK connected to the input of the onboard SI5338 on the TE0821, the signal integrity was clearly affected. We are not using the PHY_INT at all.

Thank you very much for your feedback.

Regards,

Vicente.

[JH]

Hi,
good to hear that it works now.
br
John