Author Topic: TE0741 clocking problem  (Read 347 times)


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TE0741 clocking problem
« on: October 31, 2020, 03:30:07 AM »
I want to use the GTX REFCLK1 as system clock´╝îbut  I can't assign pins to clock signals in Vivado.
Vivado displays error message as follow:
[Vivado 12-1411] Cannot set LOC property of ports, Site location is not valid ["C:/Users/Yang/Desktop/test_410t/project_1.srcs/constrs_1/new/io_constraints.xdc":20]
[DRC UCIO-1] Unconstrained Logical Port: 1 out of 4 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: sys_clk_p.


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Re: TE0741 clocking problem
« Reply #1 on: November 02, 2020, 08:11:35 AM »
this clk is connected to dedicated MGT CLK reference. You must us special buffer  to use this clock on fbga fabric. We have an example in our reference design: