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TE0807 StarterKit with SO image

Started by gergarciaa, October 17, 2020, 01:48:13 PM

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gergarciaa

Hi Folks,

Im trying to use the  TE807 Starterkit reference design as a basis for a test and just adding a DDS ip core.
My question is:

in order to use the base board (TEBF0808) is it mandatory to use a linux OS image or can i create a Standalone image?

I am actually not interested in using the PS at all so would it be possible to use the PL alone and still communicate with the baseboard and therefore not creating any image whatsoever?

Thanks in advance for your reply,
Ger

mt-user-2019

Hi GERGARCIAA,

I am not working for trenz and I am still beginner but

Quotein order to use the base board (TEBF0808) is it mandatory to use a linux OS image or can i create a Standalone image?
No it is not mandatory to have linux you can have standalone (BareMetal), freeRTOS (or other but it is not available with xilinx tools AFAIK) running on A53 Or/And R5.


QuoteI am actually not interested in using the PS at all so would it be possible to use the PL alone and still communicate with the baseboard and therefore not creating any image whatsoever?
Not 100% sure but if your clock come from the PS side you should wake up A53_0 and configure the clock. I would do at least : A53 standalone (BareMetal) with Hello world.

So the flow will be
Vivado : do the fpga side (what ever you want)
Vivado : export the xsa
Vitis : import xsa (create or update platform)
vitis : create the application Hello world

Run your hello world

Now you PS is awake with some ps -> pl clock
you can go back to vivado and play with it and reprogram the pl as long as you do not modify your clock 

BR
MT

JH

Hi MT,
thanks for your answers.

I have only a small addition to your second answer: It's not the Hello World app itself which initialised the PS-PL CLKs, it's the generated FSBL, which is also included into the Boot.bin. And in case you start Hello World with Vitis Debugger, it's a generated Xilinx script which initialise PS with setup from XSA file like the FSBL does (but in this case only Xilinx default without our FSBL changes).

br
John

gergarciaa

MT and John thanks a lot for your repply!
It helped me a lot!!

cheers you both!
Ger