Author Topic: TE0803 + 4EG // Timing constraints  (Read 455 times)

mt-user-2019

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TE0803 + 4EG // Timing constraints
« on: October 15, 2020, 02:51:35 PM »
Hello,

I am still noob with ZU+ so I probably have basic question and if those questions are not related to trenz but to xilinx feel free to inform me.

This subject will talk about synthesis  - timing

0) Overview
1) I removed the none necessary IP from your block diagram( tell me if I can remove more thing, I let pl_clko  @ 100MHz and pl_clk1 @ 25MHz)
2) I run synthesis
3) I click report clock interaction / timing summary

Since I am new with clock constraints I start with the least IP possible to be able to see if my IP is well done  and my signal well constraint but I am puzzle to see warnings and red dots in the timing area.

Do I have to set something somewhere?

mt-user-2019

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Re: TE0803 + 4EG // Timing constraints
« Reply #1 on: October 15, 2020, 02:56:42 PM »
In the constraints wizard shall I do somethings ?

I already appreciate that you read up to here.

My all goal is to have a good base where i can rely on. Because I created IP that have problems and I have 100 or 200 critical  warning or warning that I am afraid of.

I started to read already documentation about timing...

Best regards and sorry to bother.
MT

JH

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Re: TE0803 + 4EG // Timing constraints
« Reply #2 on: October 19, 2020, 07:12:03 AM »
Hi,
theoretical you can remove all IPs, it depends on things you want to do ;-)

At the moment you has only removed audio. A little bit strange is that you get timing issues now, because I've run it on my place without timing issues.
Your timing issues comes from the VIO debug core which is connected the logic of the GPIO core, in this case I think you can ignore it. VIO can be controlled via Vivado HW Manager,so that signal changes when you change signal status on GUI can be considered more or less as static.

RGPIO is only a simple interface to the CPLD, where you can control/read some signal: https://wiki.trenz-electronic.de/display/PD/TEBF0808+CPLD#TEBF0808CPLD-RGPIO

You can remove the RGPIO hierarchy, when you didn't used it. You can also remove VIO for LED control. In case you did not use DP and CAN, you can also remove the SC0808 IP (or you set DP Loc constrain in your own XDC instead to use SC0808).

br
John

mt-user-2019

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Re: TE0803 + 4EG // Timing constraints
« Reply #3 on: October 19, 2020, 09:11:58 AM »
Hello John,

Thx for you answer.

So If I remove vio_general and RGPIO I still have all the functionality of the board ( display port, usb, ehternet, SFP, sata, can)
I have little pain to see the usage of RGPIO if it is me who can control it via vivado.

BR
MT

JH

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Re: TE0803 + 4EG // Timing constraints
« Reply #4 on: October 19, 2020, 12:35:04 PM »
Hi,
Quote
So If I remove vio_general and RGPIO I still have all the functionality of the board ( display port, usb, ehternet, SFP, sata, can)
yes but there are also changes on Linux and FSBL need to bringing up all these  interfaces, see:
https://wiki.trenz-electronic.de/display/PD/TE0803+StarterKit

br
John