Author Topic: Paticularity of FMC_VADJ  (Read 328 times)

SaW

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Paticularity of FMC_VADJ
« on: October 14, 2020, 10:18:16 AM »
Good morning,
this is a follow up of this topic(Custom Mipi adapter over FMC connector), but since the question is a bit different i thought better writing a new topic.
We manufactured a test board and are testing it with the carrier TE0701 and our mipi module. As explained in the previous topic, our issue was that the I2C on the mipi module is supposed to be 3,3 volts but the mipi data lane and clock have to be of 1,2volts (xilinx specification). We are using the FMC connector to link the custom board to the carrier TE0701. So both I2C + Mipi port are driven on the same bank <=> same voltage:
- I2C is then defined with 1,2volts and will be driven to 3,3volts

To do so, we are using a voltage translator on our custom board, this one is doing the translation from 1,2volts to 3,3 volts and vice versa. The translator needs a VrefA (lower voltage) and a Vref B (higher voltage). VrefA is driven by FMC_VADJ, that we have (via the Dip switch 4) configured for 1,25 volts (SW0/1/2/3: ON/ON/OFF/OFF ) VrefB is taken from the 3,3volts of the 3,3_FMC from the pin D40 on J10A.

In the documentation of the voltage translator it is written that at normal application of the transaltor (VrefB > VrefA) a current will sync into VrefA, so into FMC_VADJ.
Is this possible? I couldnt find anything about this subject in the TRM or on the schematic.
thank you a lot for your help
Sarah

JH

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Re: Paticularity of FMC_VADJ
« Reply #1 on: October 19, 2020, 07:26:48 AM »
Hi,
which kind of level translator did you use on your FMC-card? I2C need pullup resistors and some bidirectional level translator has problems with external pullups.


Quote
In the documentation of the voltage translator it is written that at normal application of the transaltor (VrefB > VrefA) a current will sync into VrefA, so into FMC_VADJ.
Is this possible? I couldnt find anything about this subject in the TRM or on the schematic.
I'm sorry I didn't understand this question.

br
John

SaW

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Re: Paticularity of FMC_VADJ
« Reply #2 on: October 19, 2020, 09:13:46 AM »
Hi,
we manage to make it work in the end, it was a mistake on our side.
We are using the LSF0108 from texas instruments, it is a level translator made for Open-Drain and push-pull applications. We added a pullup for the output and defined the pin in the implementation design (in vivado) with pullup as well.
What i meant was that by normal fonctionnement of the translator, a small current is sent back to the voltage reference A, which, in our case, is FMC_VADJ. I was wondering is this one support it. (but i guess it does since it is working now)

Another question i have, which is not really directed to FMC_VADJ but more to custom I2C. We tried first to assign it using the xilinx IP axi-iic and the driver associated. I can send data and interact with our camera via the i2c port once linux booted, but if i trie to load the camera driver there is some issue in the communication: I should read an eeprom(using the i2c we defined previously), and it reads the 10 first registers then  tells it is not possible anymore.
I then changed to use the I2C present in the PS and redifine the in/out ports. this time the driver worked, I could read all of the register from the eeprom
Do you know what is the differnece between the 2?

thank you a lot for your help
best regards,
Sarah

JH

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Re: Paticularity of FMC_VADJ
« Reply #3 on: October 19, 2020, 12:32:34 PM »
Hi,
Quote
Do you know what is the difference between the 2?
You mean between AXI I2C IP and PS I2C over PL? Both are from Xilinx:
https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
https://www.xilinx.com/products/intellectual-property/axi_iic.html

Either there is a misconfiguration of the AXI-I2C IP or you has a timing issue or some driver problems.

br
John