Author Topic: TE0726-03M and Ethernet via EMIO  (Read 353 times)

FpgaJohn

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TE0726-03M and Ethernet via EMIO
« on: October 07, 2020, 01:32:45 AM »
Hi,

So I purchased a Trenz Zynqberry TE0726-03M board and was able to get a couple of demo's working and running.  Now I am new to the Zynq platform and am trying to understand what the difference between MIO and EMIO connectors are, and what they have to do with the FPGA.

In a nutshell, I create a Zynqberry project using Vivado 2019.1, with a block design containing a Zynq Processing System.

I then double-click on the Zynq block and set:
* MIO Configuration => I/O Peripherals -> ENET 0 to EMIO
* MIO Configuration => I/O Peripherals -> ENET 0 -> MDIO to EMIO

After doing this, I see a bunch of pins on my Zynq Processing Block that look like a GMII connection, only thing I don't understand what they are for!
* Can I send or receive data using them?

Also, can I map pins on the FPGA directly to the EMIO? Any tips or pointers are appreciated! (I have been scanning through Xilinx documentation but I can't find the connection)

The pins I see are:
* GMII_ETHERNET_0
 * ENET0_GMII_TX_EN[0:0]  out
 * ENET0_GMII_TX_ER[0:0]  out
 * ENET0_GMII_TXD[7:0]  out
 * ENET0_GMII_COL  in
 * ENET0_GMII_CRS  in
 * ENET0_GMII_RX_CLK  in
 * ENET0_GMII_RX_DV  in
 * ENET0_GMII_RX_ERR  in
 * ENET0_GMII_TX_CLK  in
 * ENET0_GMII_RXD[7:0]  in

JH

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Re: TE0726-03M and Ethernet via EMIO
« Reply #1 on: October 07, 2020, 07:27:42 AM »
Hi,
we offer reference designs and demo designs for TE0726:
https://wiki.trenz-electronic.de/display/PD/TE0726+Reference+Designs
On TE0726, ETH is realized over USB interface and USB/ETH HUB. Additional Linux settings are need to support this, see reference design documentation.


MIO are dedicated IOs for dedicated PS Periphery.  Some of these interface (ETH is one of them where it's possible to use EMIO) can be changed to EMIO, so that you can use them over PL and PL IOs. For more details, see:
https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#documentation

Some note: Wen you want to use external ETH PHY, depending on your PHY and how you has connect it to PL IOs, you must add maybe GMII to RGMII IP from Xilinx. And ETH has also some restriction regarding trace length and impedance, so you must pay attention how you want to connect it to Zynqberry.


br
John
« Last Edit: October 07, 2020, 07:32:50 AM by JH »